Proper PCB layout is critical for achieving the full performance benefits of Rohm SiC power devices. This guide covers layout techniques to minimize parasitic inductance.

Minimizing Parasitic Inductance: Parasitic inductance in power loops causes voltage overshoot during switching. Minimize the area of the power loop by placing components close together.

Gate Loop Design: The gate drive loop must have minimal inductance for clean switching. Place the gate driver as close as possible to the MOSFET. Use Kelvin source connection to eliminate source inductance from the gate loop.

Thermal Considerations: Use adequate copper area for heat spreading from device terminals. Implement thermal vias under device pads to conduct heat to inner layers.

EMI and Safety: Minimize loop areas to reduce EMI radiation. Maintain adequate creepage and clearance distances for the voltage rating.