Aurasemi Clock Chips

Clock generators (synthesizers) create clock signals from a reference crystal or oscillator, generating multiple output frequencies using PLL technology. They are ideal when you need to generate various clock frequencies from a single crystal reference. Jitter attenuators (cleaners) accept an existing clock input with high jitter and output a cleaned, low-jitter version using high-performance PLLs with narrow loop bandwidth. They are essential when receiving clock signals from long traces or noisy environments. Aurasemi offers both types: AU50xx series clock generators for frequency synthesis and AU54xx series jitter attenuators for jitter cleaning applications.

Use clock generators for frequency synthesis; use jitter attenuators for cleaning noisy clock signals.

Jitter specifications in Aurasemi clock chips include: (1) RMS jitter - the root-mean-square of phase noise integrated over a frequency range (typically 12kHz to 20MHz), measured in femtoseconds (fs). Lower values indicate cleaner clocks. Aurasemi's AU5425 achieves <100fs RMS jitter

(2) Peak-to-peak jitter - the maximum deviation over time, important for synchronous systems

(3) Phase noise - measured in dBc/Hz at specific offsets from the carrier, showing noise distribution across frequencies. For high-speed SerDes (10G+), RMS jitter <500fs is typically required. For precision ADC/DAC applications, <100fs may be needed. Check your system's jitter tolerance specifications when selecting.

Select clock chips based on your system's jitter requirements - <100fs for high-performance, <500fs for general high-speed.

Aurasemi clock chips support multiple output types: (1) LVDS (Low-Voltage Differential Signaling) - 3.5mA current-mode differential outputs, low power, good for general-purpose high-speed clocking

(2) LVPECL (Low-Voltage Positive Emitter-Coupled Logic) - high-speed differential outputs with excellent jitter performance, ideal for 10G+ networking

(3) HCSL (High-Speed Current Steering Logic) - low-power differential outputs specifically designed for PCIe clocking

(4) CMOS/LVTTL - single-ended outputs for lower frequency or cost-sensitive applications

(5) CML (Current Mode Logic) - used for very high-speed SerDes clocking. Many Aurasemi devices support multiple output types through pin configuration or register settings for design flexibility.

Choose LVPECL/HCSL for high-speed differential, LVDS for general-purpose, CMOS for single-ended applications.

Proper power supply design is critical for clock performance: (1) Use clean, low-noise power supplies - Aurasemi clock chips typically require 1.8V, 2.5V, or 3.3V with <50mV ripple

(2) Implement proper decoupling - place 0.1μF and 1μF ceramic capacitors close to each power pin, with the smaller capacitor closest to the pin

(3) Use separate power planes - isolate analog (PLL) and digital power supplies if possible

(4) Add ferrite beads - series ferrite beads on power lines can help isolate noise

(5) Grounding - use solid ground planes and minimize ground loops

(6) For multi-rail devices, follow the recommended power-up sequence in the datasheet. Poor power supply design can degrade jitter performance by 2-3x.

Use clean power with proper decoupling to achieve specified jitter performance.

Optimal PCB layout for Aurasemi clock chips: (1) Keep crystal/oscillator traces short - minimize length between crystal and chip (<10mm ideal)

(2) Differential routing - route differential clock pairs with matched length and controlled impedance (100Ω for LVDS/LVPECL)

(3) Avoid vias - minimize vias on critical clock traces

(4) Ground planes - use continuous ground planes under clock circuits

(5) Isolation - keep clock traces away from switching power supplies and high-speed digital signals

(6) Termination - place termination resistors close to load devices

(7) Thermal design - ensure adequate copper area for thermal dissipation. Following these guidelines helps achieve the specified jitter performance and signal integrity.

Follow differential routing best practices and minimize trace lengths for optimal clock performance.