AU5425
Ultra-low jitter clock generator with <100fs RMS jitter, 1MHz to 2.1GHz output range, and flexible frequency planning...
Product Overview
Description
The AU5425 is a high-performance clock generator designed for demanding networking and communication applications. It features an integrated high-performance PLL that generates ultra-low jitter clock outputs from a crystal or reference clock input.
With RMS jitter performance below 100 femtoseconds (12kHz to 20MHz integration), the AU5425 meets the stringent requirements of 100G/400G Ethernet, high-speed ADC/DAC systems, and FPGA clocking applications. The device provides four differential outputs configurable as LVDS, LVPECL, or HCSL.
The AU5425 supports output frequencies from 1MHz to 2.1GHz through an I2C/SPI programmable interface. It operates from a 1.8V, 2.5V, or 3.3V supply and is available in a compact 5x5mm QFN package.
Product Series
AU
Primary Application
100G/400G Ethernet switches and routers
Key Features
- Ultra-low <100fs RMS jitter performance
- Wide 1MHz to 2.1GHz output frequency range
- Four configurable differential outputs
- Flexible LVDS/LVPECL/HCSL output types
- I2C/SPI programmable interface
- Integer and fractional PLL modes
- Hitless switching between references
- Industrial temperature range -40°C to +85°C
Specifications
| Output Frequency | 1MHz to 2.1GHz |
|---|---|
| RMS Jitter | <100fs (12kHz-20MHz) |
| Outputs | 4 differential |
| Output Types | LVDS/LVPECL/HCSL |
| Input | Crystal or reference clock |
| Supply Voltage | 1.8V/2.5V/3.3V |
| Interface | I2C/SPI |
| Package | 5x5mm QFN-32 |
Applications
100G/400G Ethernet switches and routers
Communication and interface
5G base station and small cell equipment
Electronic system design
High-speed ADC/DAC clocking
Data acquisition and conversion
FPGA and ASIC clock distribution
Electronic system design
Optical transport networks
Communication and interface
Test and measurement equipment
Data acquisition and conversion
FAE Expert Insights
"The AU5425 is my go-to recommendation for customers needing ultra-low jitter clocking. In my experience supporting 5G and data center designs, this device consistently delivers the <100fs jitter performance needed for 100G+ SerDes applications. I particularly appreciate the flexible output configuration - being able to switch between LVDS, LVPECL, and HCSL through register settings saves board space and simplifies BOM management. The I2C interface makes it easy to fine-tune frequencies during bring-up. One tip: pay close attention to power supply noise - use a dedicated LDO for the PLL supply to achieve the best jitter performance. I've seen customers achieve 80-90fs typical jitter with clean power design."
Ultra-low jitter clock generator ideal for 100G+ networking and 5G applications
— Michael Chen, BeiLuo
Frequently Asked Questions
What is the typical jitter performance of AU5425 in real applications?
In typical applications with proper PCB layout and clean power supply, the AU5425 achieves 80-90fs RMS jitter (12kHz to 20MHz integration). The datasheet specifies <100fs as a maximum guarantee, but most devices perform significantly better. Factors affecting jitter include: power supply noise (use dedicated LDO), PCB layout (follow differential routing guidelines), temperature (performance is stable across -40°C to +85°C), and output loading (maintain proper termination). For the lowest jitter, use the LVPECL output mode and ensure the crystal reference has low phase noise (<-150dBc/Hz at 1kHz offset).
Expect 80-90fs typical jitter with good design practices; <100fs guaranteed.
How do I program the output frequency of AU5425?
The AU5425 supports frequency programming through I2C or SPI interface: (1) Calculate PLL parameters using Aurasemi's Clock Architect software or manual calculation; (2) Write divider values to registers 0x00-0x0F for the four output channels; (3) Configure output type (LVDS/LVPECL/HCSL) in register 0x10; (4) Enable outputs by writing to register 0x11; (5) Lock the PLL by setting register 0x12. The device supports integer and fractional PLL modes. For fractional mode, set the fractional divider in registers 0x20-0x23. The default power-on frequency is determined by external strapping pins, allowing operation without programming if the default meets your requirements.
Use I2C/SPI interface to program output frequencies; default strapping available for common frequencies.
What crystal specifications are recommended for AU5425?
Recommended crystal specifications for AU5425: (1) Frequency - 25MHz or 50MHz are most common, but 10MHz to 50MHz range is supported; (2) Load capacitance - 8pF to 20pF, match to your PCB design; (3) ESR - <50Ω for reliable startup; (4) Drive level - 100μW typical, 200μW maximum; (5) Frequency stability - ±20ppm for general applications, ±10ppm for high-performance; (6) Aging - ±3ppm/year maximum; (7) Package - HC-49/S or compact 3.2x2.5mm SMD. For best jitter performance, select a crystal with low phase noise. Aurasemi recommends crystals from Epson, NDK, or TXC. The crystal should be placed close to the AU5425 (<10mm trace length) with proper load capacitors.
Use 25MHz or 50MHz crystal with <50Ω ESR and ±20ppm stability for best performance.
Can AU5425 be used for PCIe clocking applications?
Yes, the AU5425 can be used for PCIe clocking with proper configuration: (1) Set output type to HCSL for PCIe compliance; (2) Configure 100MHz output frequency (PCIe Gen1/Gen2/Gen3) or 25MHz reference; (3) Enable spread spectrum clocking (SSC) by setting register 0x15 to 0x03 for -0.5% downspread; (4) Ensure <3ps cycle-to-cycle jitter for PCIe Gen3 compliance; (5) Use proper HCSL termination (50Ω to ground on each output). However, for dedicated PCIe applications, Aurasemi recommends the AU5061 PCIe clock generator which includes built-in PCIe compliance features, reference clock inputs, and simpler configuration. The AU5425 is better suited as a general-purpose clock generator that can also support PCIe among other protocols.
AU5425 can support PCIe; consider AU5061 for dedicated PCIe applications with built-in compliance features.
What is the power consumption of AU5425?
AU5425 power consumption varies by configuration: (1) Core power - 45mA typical at 3.3V with all outputs enabled at 100MHz; (2) Output power - 15mA per LVDS pair, 25mA per LVPECL pair, 20mA per HCSL pair; (3) Total power - typically 150-200mW depending on output configuration and frequency; (4) Power-down mode - <10μA when disabled via I2C; (5) Individual output enable/disable - save power by disabling unused outputs. For power-sensitive applications, use LVDS outputs (lower power than LVPECL), disable unused outputs, and consider the 1.8V supply option (reduces power by ~30%). Thermal design should accommodate up to 250mW worst-case power dissipation.
Typical 150-200mW; use 1.8V supply and disable unused outputs to minimize power.