Chipanalog Isolated Gate Drivers

Miller clamp is a feature that prevents false turn-on of power devices during high dV/dt switching. During turn-off, the Miller capacitance (Cgd) can couple current into the gate, potentially raising gate voltage above threshold and causing unwanted turn-on. The Miller clamp provides a low-impedance path to ground when gate voltage drops below a threshold (typically 2V), preventing this false turn-on. This is critical in bridge topologies where shoot-through could destroy the power devices. Chipanalog's CA-IS3211 includes active Miller clamp for reliable operation.

Use gate drivers with Miller clamp for bridge topologies and high dV/dt applications. Contact our FAE team for gate driver selection.

Desaturation detection monitors the collector-emitter (or drain-source) voltage of the power device during conduction. If the device enters saturation (high voltage drop), indicating overcurrent or short-circuit, the detection circuit triggers a soft turn-off sequence to protect the device. This prevents catastrophic failure from hard switching during fault conditions. Chipanalog's CA-IS3211 includes desaturation detection with configurable blanking time and soft turn-off, providing comprehensive IGBT protection.

Use desaturation detection for IGBT applications requiring overcurrent protection. Contact our FAE team for protection configuration.

Gate driver peak current is calculated based on gate charge and desired switching time. The formula is: Ipeak = Qg / tsw, where Qg is total gate charge from datasheet and tsw is desired switching time. For example, with Qg = 100nC and desired switching time of 100ns: Ipeak = 100nC / 100ns = 1A. Add 20-30% margin for reliable operation. Also consider: Gate resistance affects actual current

Driver output impedance limits peak current

and Higher peak current enables faster switching but increases EMI.

Calculate peak current based on gate charge and switching time. Contact our FAE team for gate driver sizing assistance.

Propagation delay in gate drivers affects switching timing and dead time in bridge topologies. Shorter propagation delay (typically 50-100ns) allows: More precise dead time control

Higher switching frequencies

Better synchronization in multi-phase systems

and Reduced dead time losses. However, very fast drivers can cause more EMI. Chipanalog gate drivers offer propagation delays of 70-100ns with excellent matching between channels (<10ns), enabling precise timing control in half-bridge and full-bridge applications.

Select gate drivers with propagation delay matching your switching frequency requirements. Contact our FAE team for timing analysis.

Dead time prevents shoot-through in half-bridge topologies by ensuring both high-side and low-side switches are never on simultaneously. Set dead time based on: Power device turn-off time (from datasheet)

Propagation delay variation

and Safety margin (typically 100-200ns). Chipanalog's CA-IS3221 includes programmable dead time (via external resistor) from 100ns to several microseconds. Calculate: Minimum dead time = Td(off,max) + propagation delay variation + safety margin. For example, with Td(off) = 300ns, variation = 50ns, margin = 100ns: Set dead time to 450ns minimum.

Calculate dead time based on device characteristics and margins. Contact our FAE team for dead time optimization.