Analog Devices Data Converters

SAR (Successive Approximation Register) and Sigma-Delta ADCs use different architectures suited for different applications: SAR ADCs provide high-speed conversion with low latency, making them ideal for multiplexed systems and control loops. They offer excellent DC accuracy and are available up to 20-bit resolution. Conversion times are typically microseconds, and power consumption scales with sampling rate. Sigma-Delta ADCs use oversampling and noise shaping to achieve very high resolution (up to 32 bits) with integrated digital filtering. They excel in precision measurement applications but have higher latency due to digital filtering. Sigma-Delta converters often include integrated PGAs and reference buffers, reducing external component count. Choose SAR for speed and multiplexing

choose Sigma-Delta for maximum resolution and integrated signal conditioning.

Use SAR ADCs for high-speed multiplexed systems; use Sigma-Delta for high-resolution precision measurement with integrated filtering.

ENOB is the actual performance of an ADC accounting for noise and distortion. Calculate ENOB from the measured SNR: ENOB = (SNR - 1.76) / 6.02, where SNR is in dB. For example, an ADC with 90dB SNR has ENOB = (90 - 1.76) / 6.02 = 14.7 bits. Factors that reduce ENOB include clock jitter, reference noise, and input signal conditioning. To maximize ENOB: 1) Use low-jitter clock sources

2) Implement proper anti-aliasing filters

3) Optimize reference voltage quality

4) Ensure good PCB layout with proper grounding

5) Use dithering for low-amplitude signals. ADI datasheets specify both SNR and typical ENOB at various input frequencies to help you select the right converter for your dynamic range requirements.

Calculate required ENOB from your dynamic range requirements; add 2-3 bits margin for real-world performance degradation.

Sampling rate selection follows the Nyquist theorem - sample at least twice the highest frequency of interest. However, practical designs require oversampling for several reasons: 1) Anti-aliasing filter roll-off - higher sampling rates allow simpler, lower-order filters

2) Processing gain - oversampling improves SNR by 3dB (0.5 bit) for every doubling of sample rate

3) Digital filter requirements - Sigma-Delta ADCs need high oversampling ratios (typically 64x to 256x)

4) System timing - consider latency requirements in control loops. For audio (20kHz bandwidth), 48-96kSPS is standard. For industrial sensors (1kHz bandwidth), 10-100kSPS is typical. For communications, sample at 2.5x to 4x the signal bandwidth to ease filter requirements. Always include margin for future requirements.

Sample at 2.5x to 4x your signal bandwidth; use higher oversampling for Sigma-Delta ADCs (64x-256x).

High-speed ADCs use several interface options for FPGA connectivity: 1) Parallel LVDS - traditional interface for ADCs up to ~500MSPS, requires many IO pins

2) JESD204B/C - high-speed serial interface using 1-8 lanes at up to 28Gbps, standard for GSPS ADCs

3) SPI - for lower-speed configuration and control

4) I2C - for slow control interface. For JESD204B designs, the FPGA must include dedicated transceivers (GTX/GTH/GTY in Xilinx, GX/GT in Intel). Key considerations include: lane rate matching, deterministic latency requirements, SYSREF synchronization for multi-device systems, and proper clock distribution. ADI provides FPGA reference designs and JESD204B IP cores for major FPGA vendors. The interface choice depends on ADC sampling rate, FPGA capabilities, and PCB routing constraints.

Use JESD204B for GSPS ADCs; use parallel LVDS for <500MSPS if FPGA lacks high-speed transceivers.

The reference voltage determines ADC full-scale range and directly impacts accuracy. Selection criteria include: 1) Initial accuracy - choose reference with tight tolerance (0.1% or better) for absolute accuracy

2) Temperature drift - critical for industrial applications, select <10ppm/°C for precision

3) Noise - reference noise adds directly to ADC noise, choose low-noise references (<10μVp-p)

4) Load regulation - ensure reference maintains accuracy under ADC reference current transients

5) Long-term stability - important for calibration-free operation. ADI offers precision references like ADR43xx series with excellent drift and noise specifications. For highest accuracy, use the ADC's internal reference if available, or buffer external references with precision op-amps. Always include proper decoupling capacitors close to the ADC reference pins.

Select reference with <10ppm/°C drift and <10μVp-p noise for precision applications; use internal reference when available.