PSLDO50
High-PSRR 500mA LDO with low noise, fast transient response for sensitive analog circuits
Product Overview
Description
The PSLDO50 is a high-performance low-dropout voltage regulator designed for noise-sensitive analog and RF applications.
With high PSRR of 80dB at 1kHz and low output noise of 30uVrms, this LDO provides clean power for precision analog circuits.
The device features fast transient response, low dropout voltage of 200mV at 500mA, and excellent line and load regulation.
Product Series
PSLDO
Primary Application
Precision analog circuits
Key Features
- High PSRR: 80dB at 1kHz
- Low output noise: 30uVrms
- Low dropout voltage: 200mV at 500mA
- Fast transient response
- Low quiescent current: 80uA
- Multiple fixed output options
- Current limit and thermal protection
- Excellent line and load regulation
- Small package options
Specifications
| Input Voltage | 2.5V - 5.5V |
|---|---|
| Output Current | 500mA max |
| Output Voltage | Fixed 1.8V, 2.5V, 3.3V, 5V or adjustable |
| Dropout Voltage | 200mV @ 500mA |
| PSRR | 80dB @ 1kHz, 60dB @ 100kHz |
| Output Noise | 30uVrms (10Hz - 100kHz) |
| Quiescent Current | 80uA typical |
| Line Regulation | 0.02%/V |
| Load Regulation | 0.3%/A |
| Temperature Range | -40°C to +85°C (Industrial), -40°C to +125°C (Automotive) |
| Package | SOT-23-5, SOT-89, DFN-6 |
Applications
Precision analog circuits
Electronic system design
RF and communication systems
Communication and interface
Sensor power supplies
Sensor signal conditioning
ADC and DAC reference supplies
Data acquisition and conversion
Medical instrumentation
Medical electronics
Audio equipment
Electronic system design
Camera and imaging systems
Electronic system design
FAE Expert Insights
"The PSLDO50 is my top recommendation for sensitive analog applications. The 80dB PSRR at 1kHz effectively rejects switching noise from upstream converters, making it ideal for powering precision ADCs and DACs. I've used this LDO in medical imaging applications where the 30uVrms noise level is critical for image quality. The fast transient response handles load steps from ADC sampling without significant voltage droop. For best noise performance, I recommend adding a 10nF bypass capacitor at the BYP pin and keeping the output capacitor close to the load. The low quiescent current is also great for battery-powered portable equipment."
Excellent PSRR and low noise for sensitive analog applications
— Jennifer Liu, BeiLuo
Frequently Asked Questions
What is PSRR and why is it important for LDOs?
PSRR (Power Supply Rejection Ratio) measures how well an LDO rejects noise and ripple from the input power supply. It is expressed in dB, with higher values indicating better rejection. The PSLDO50 achieves 80dB PSRR at 1kHz, meaning it attenuates input noise by a factor of 10,000 at that frequency. This is critical for sensitive analog circuits like ADCs, DACs, and RF systems that require clean power. High PSRR prevents switching noise from upstream converters from affecting analog performance.
Select LDOs with PSRR >60dB at your critical frequencies. The PSLDO50 excels at audio and ADC sampling frequencies.
How does dropout voltage affect LDO performance?
Dropout voltage is the minimum input-output voltage differential required for the LDO to maintain regulation. The PSLDO50 has a low dropout of 200mV at 500mA, allowing it to regulate even when the input is only 200mV above the desired output. This is important for battery-powered applications where maximizing battery life requires operating until the battery voltage drops close to the output voltage. Lower dropout voltage extends battery life and reduces power dissipation.
Choose LDOs with dropout voltage lower than your minimum input-output headroom. The PSLDO50 is ideal for 3.3V output from Li-ion batteries.
What capacitors are recommended for the PSLDO50?
For the PSLDO50, use a 1uF to 10uF ceramic output capacitor with X5R or X7R dielectric for stability. The capacitor should be placed close to the output pin. For improved transient response, use larger output capacitance (22uF to 47uF). An optional 10nF bypass capacitor at the BYP pin reduces output noise. Use low-ESR ceramic capacitors for best performance. The input capacitor (1uF to 10uF) helps reject input noise and should be placed close to the input pin.
Start with 10uF output and 1uF input capacitance. Add bypass capacitor for lowest noise. Our FAE team can optimize for your specific requirements.
How do I minimize output noise from the PSLDO50?
To minimize output noise: 1) Use the BYP pin with a 10nF capacitor to ground - this creates a low-pass filter for the internal reference; 2) Use larger output capacitance (22uF or more) to filter high-frequency noise; 3) Keep the PCB layout clean with short traces and good grounding; 4) Use an additional RC filter (10Ω + 10uF) at the output for ultra-sensitive applications; 5) Ensure the input supply is clean - the LDO can only reject noise, not eliminate it. These techniques can achieve output noise below 20uVrms.
Use bypass capacitor for best noise performance. For ultra-low noise, add external RC filter. Contact our FAE team for noise-critical applications.
What is the thermal performance of the PSLDO50?
The PSLDO50 includes thermal shutdown protection at 165°C junction temperature with 15°C hysteresis. The maximum power dissipation depends on the package and thermal resistance. For the SOT-89 package with thermal resistance of 150°C/W, the maximum power dissipation is about 600mW at 25°C ambient. For higher currents or larger dropout voltages, use the DFN package with better thermal performance or add a small heatsink. Calculate junction temperature using: Tj = Ta + (Pd × Rthja), where Pd = (Vin - Vout) × Iout.
Calculate power dissipation and junction temperature for your application. Use DFN package for higher power or contact our FAE team for thermal solutions.