NSi6602

The NSi6602 supports switching frequencies up to 1MHz, though practical limits depend on gate drive power dissipation and PCB thermal design. At 1MHz switching with 10nC gate charge (typical for 60A SiC MOSFET), the average gate drive power is approximately 1W per channel. This requires careful thermal management with proper heat sinking or thermal vias to the ground plane. In practical motor drive applications at 20kHz switching, the NSi6602 operates well within thermal limits with minimal heatsinking. For high-frequency applications above 100kHz, I recommend calculating gate drive power as P = Qg x Vdd x fsw, and ensuring your thermal design maintains junction temperature below 125C. The 65ns propagation delay also contributes to switching losses - at 500kHz, each switching transition is 3% of the switching period.

For motor drives at 10-50kHz, NSi6602 is ideal with minimal thermal concerns. For very high frequency applications above 200kHz, ensure proper thermal design and consider additional heat spreading techniques.

Desaturation detection monitors the power switch collector-emitter voltage (or drain-source voltage) during conduction to detect fault conditions like shoot-through or device failure. When the monitored voltage exceeds the internal reference (typically 7V), the driver initiates a soft turn-off sequence to gracefully discharge the gate and avoid high dV/dt transients. Key implementation considerations: Connect the DESAT pin to the switch collector through a series resistor (typically 100 ohms) and diode. The blanking time (typically 300ns) prevents false trips during initial turn-on transients. Ensure the desaturation threshold matches your switch voltage drop at rated current plus margin. For IGBTs with higher VCE(sat), you may need to adjust the blanking time or use external desaturation circuits. The soft turn-off feature gradually reduces gate voltage over 2-3us, preventing the large dV/dt that could couple noise into the driver input.

Use the recommended DESAT circuit in the datasheet for most applications. For higher VCE(sat) IGBTs, increase blanking time or use external DESAT comparator. Verify desaturation response under your worst-case load conditions.

Gate resistor selection balances switching speed, EMI, and switching loss trade-offs. For NSi6602 driving SiC MOSFETs: For switching frequencies <50kHz where efficiency is priority, use lower gate resistors (2-5 ohms) to minimize switching losses. For switching frequencies >100kHz where EMI is critical, use higher gate resistors (10-20 ohms) to slow transitions and reduce overshoot/ringing. The 6A sink current capability allows even lower gate resistance than drivers with limited sink current. Calculate approximate switching loss reduction: Reducing Rg from 10 ohms to 5 ohms typically reduces switching losses by 20-30% but increases turn-off dV/dt. I recommend starting with 5 ohms for SiC MOSFETs and optimizing based on observed waveforms and EMI measurements. Always verify peak gate current doesn't exceed driver ratings - for 60A SiC MOSFET with 25nC gate charge, peak current is approximately 6A at 5V/5ohm = 1A plus transients.

Start with 5 ohms for SiC MOSFETs at 20kHz switching. Adjust based on switching waveform measurements - increase Rg if you see excessive overshoot, decrease if switching losses are too high.

In half-bridge configurations, when the high-side switch turns off, the rapid dV/dt on the switching node can couple through the Miller capacitance (Cgd) of the low-side device, causing a voltage spike on the gate that can falsely turn on the device. The active Miller clamp provides a low-impedance path to ground for this displacement current, preventing the gate voltage from exceeding the threshold. The NSi6602 features a dedicated Miller clamp pin (CLAMP) that connects internally to the gate driver output when the main output is low. The Miller clamp turn-on threshold is typically 2V, providing protection before the device threshold is reached. For very high dv/dt applications (>50kV/us), I recommend adding an external gate-to-source resistor (typically 10k ohms) in parallel with the Miller clamp for additional safety margin.

For half-bridge configurations with high dv/dt, always use the active Miller clamp feature. Add external 10k gate-source resistor for added protection in demanding SiC applications. Verify Miller clamp operation with high dv/dt stress testing.

Under-voltage lockout (UVLO) prevents the driver from providing insufficient gate voltage, which would cause the power switch to operate in the linear region with excessive heat generation. The NSi6602 UVLO activates at approximately 9V on VDD, with 1V hysteresis to prevent oscillation at the threshold. During UVLO condition, the output is forced low, ensuring the power switch turns off safely. Key considerations: The 9V UVLO threshold is suitable for SiC MOSFETs with 12V or 15V gate drive. For SiC MOSFETs requiring 18V drive, ensure your VDD supply is stable above 18V with margin to the UVLO threshold. During power-up, the UVLO ensures the low-side device (if configured) remains off until the driver has sufficient voltage. This prevents cross-conduction in half-bridge configurations during startup. The UVLO also provides protection during supply voltage dips or brown-out conditions common in industrial environments.

For 12V gate drive systems, verify VDD stays above 10V under all conditions including brown-out. For 15V systems, ensure adequate supply margin. Use UVLO fault output to inform the controller of driver supply issues.