LKS_GD_6N_1A5

Bootstrap capacitor sizing calculation: (1) Minimum capacitance - Cboot > 2 × (2Qg + Iq/fsw + Qls), where Qg is high-side MOSFET gate charge, Iq is quiescent current, fsw is switching frequency, Qls is level shift charge; (2) Typical values - 10uF for small MOSFETs (Qg<50nC), 22uF for medium (Qg 50-100nC), 47uF for large (Qg>100nC); (3) Voltage rating - 2× bootstrap voltage, typically 25V or 35V; (4) Type - X5R or X7R ceramic capacitor for low ESR; (5) Placement - close to driver pins with short traces. Undersized capacitor causes insufficient gate voltage and high switching losses. Oversized capacitor slows charging and may exceed charging time limits.

Start with 22uF for typical applications. Calculate based on Qg and switching frequency.

Gate oscillation prevention techniques: (1) Gate resistor - series resistor (typically 5-20Ω) dampens oscillations, limits di/dt; (2) Loop inductance - minimize gate drive loop area, use Kelvin connections; (3) PCB layout - keep gate traces short and wide, avoid vias in gate path; (4) Gate capacitance - small capacitor (100pF-1nF) from gate to source can dampen high-frequency ringing; (5) Ferrite bead - series ferrite bead blocks high-frequency oscillations. Gate oscillations cause EMI, excessive switching losses, and MOSFET damage. They are caused by parasitic inductance resonating with MOSFET capacitance. Proper layout is more important than component values - minimize loop inductance first.

Use 10Ω gate resistor. Minimize loop inductance through proper PCB layout.

Dead-time selection guidelines: (1) Purpose - prevents shoot-through by ensuring one MOSFET is fully off before other turns on; (2) Minimum - must exceed MOSFET turn-off time (typically 100-500ns); (3) Maximum - excessive dead-time causes body diode conduction, efficiency loss; (4) Typical values - 500ns to 2us for IGBT, 200ns to 1us for MOSFET; (5) Temperature - MOSFETs switch slower at high temperature, increase dead-time margin; (6) Optimization - start conservative (1-2us), reduce while monitoring efficiency and temperature. Linco drivers have programmable dead-time. The optimal dead-time balances shoot-through protection with efficiency. Measure switching waveforms to verify adequate dead-time.

Start with 1us dead-time. Reduce while monitoring efficiency. Never below 200ns.

MCU interface to gate driver: (1) Input signals - typically 3.3V or 5V logic level inputs for HIN/LIN (high/low side inputs); (2) Level translation - Linco drivers accept 3.3V logic even with 12V supply; (3) PWM frequency - driver supports up to 100kHz PWM, limited by propagation delay; (4) Isolation - for high-voltage applications, use optocouplers or digital isolators between MCU and driver; (5) Fault feedback - connect driver fault output to MCU GPIO for protection monitoring; (6) Enable control - use driver enable pin for system-level shutdown. The interface is straightforward for low-voltage systems. For high-voltage or safety-critical applications, add isolation between MCU and driver.

Direct connection for low voltage. Use isolation for high voltage or safety applications.

Gate driver thermal management: (1) Power dissipation - Pd = Qg × Vgs × fsw × 6 (for 6N driver), example: 100nC × 12V × 20kHz × 6 = 144mW; (2) Junction temperature - Tj = Ta + Pd × Theta-JA, ensure Tj < 125°C; (3) PCB design - thermal vias under package, copper area for heat spreading; (4) Switching frequency - higher fsw increases dissipation significantly; (5) MOSFET gate charge - larger Qg increases driver dissipation. Gate drivers typically don't require heatsinks, but proper PCB thermal design is important. The main heat source is charging/discharging MOSFET gate capacitance. For very high frequencies (>50kHz) or large MOSFETs, verify thermal calculations.

Calculate power dissipation from Qg and fsw. Ensure Tj < 125°C with proper PCB design.