Giantec NOR Flash

Giantec offers NOR Flash products with densities ranging from 1Mbit to 128Mbit to meet different application requirements: Low density (1Mbit to 8Mbit) for small firmware, bootloaders, and parameter storage. Medium density (16Mbit to 32Mbit) for typical embedded applications and moderate code sizes. High density (64Mbit to 128Mbit) for large firmware, multiple images, and data logging. The most popular densities are 16Mbit (2MB) and 32Mbit (4MB) which provide sufficient storage for most embedded Linux and RTOS applications. When selecting density, consider: Current firmware size plus 30-50% for future growth. Need for multiple firmware images (active + backup). Data logging or user storage requirements. Bootloader and configuration space. Giantec's pin-compatible packages within the same density family allow easy upgrades.

Select density based on firmware size plus 30-50% margin. Contact our FAE team for density planning.

Giantec NOR Flash differs from NAND Flash in several key aspects: NOR Flash advantages: Random access capability - can read any byte directly. Execute-In-Place (XIP) - CPU can execute code directly from Flash. Fast read speeds - comparable to RAM for code execution. Better reliability - lower bit error rates, longer life. Simpler interface - standard SPI, easy to use. NAND Flash advantages: Higher density - Gbits to Tbits vs Mbits for NOR. Lower cost per bit - more economical for bulk storage. Faster write/erase - better for frequent updates. Use NOR Flash for: Firmware and code storage. Applications requiring XIP. Bootloaders and initialization code. Small to medium data storage. Use NAND Flash for: Mass data storage (images, video, logs). Applications with frequent write operations. Cost-sensitive high-density applications. Many systems use both: NOR for boot code, NAND for data storage.

Use NOR Flash for code execution, NAND for mass storage. Contact our FAE team for Flash selection guidance.

Execute-In-Place (XIP) is a feature of NOR Flash that allows a CPU to execute program code directly from the Flash memory without copying it to RAM first. This capability is unique to NOR Flash and not available in NAND Flash. How XIP works: The NOR Flash is memory-mapped into the CPU's address space. The CPU can fetch instructions directly from Flash using standard read cycles. No RAM is required for code storage, reducing system cost. Data can still be read and written normally. XIP advantages: Reduces RAM requirements - only data needs RAM. Lower system cost - less RAM needed. Faster boot time - no code copying required. Simpler software - no memory management for code. XIP considerations: NOR Flash read speed is slower than RAM (affects performance). XIP is read-only - code cannot modify itself. Best for: Bootloaders, initialization code. Systems with limited RAM. Cost-sensitive applications. For best performance, frequently executed code can be copied to RAM (shadowing) while less critical code runs from Flash.

Use XIP to reduce RAM requirements. Contact our FAE team for XIP system design.

Giantec NOR Flash supports flexible erase and program operations: Erase operations: Sector erase - erases a sector (typically 4KB or 64KB) to all 1s. Chip erase - erases the entire device (slower, used sparingly). Erase is required before programming - can only change 1s to 0s. Program operations: Byte program - programs individual bytes. Page program - programs multiple bytes (typically 256 bytes). Program changes 1s to 0s - cannot program 0s to 1s without erase. Typical operation sequence: Erase the sector(s) containing target address. Program new data to the erased locations. Verify programmed data. Key specifications: Erase time: typically 100ms-500ms per sector. Program time: typically 0.5ms-2ms per page. Endurance: typically 100,000 erase/program cycles. For applications with frequent updates, consider: Wear leveling to distribute writes across sectors. EEPROM for frequently changing small data. File systems designed for Flash (JFFS2, LittleFS).

Erase before program. Use wear leveling for frequent updates. Contact our FAE team for Flash management strategies.

Giantec NOR Flash products offer high-speed read operations suitable for code execution and fast data access: Standard SPI read: up to 50MHz clock, 6.25MB/s throughput. Fast read (dual output): up to 80MHz effective, 10MB/s throughput. Quad SPI read: up to 80MHz effective, 20MB/s throughput. XIP mode: sustained random read access for code execution. The actual read speed depends on: SPI clock frequency configured. Read mode (standard, dual, quad). MCU SPI peripheral capabilities. PCB layout and signal integrity. For code execution (XIP): Random read access is fast enough for most embedded CPUs. Cache systems can improve performance for frequently executed code. Consider shadowing critical code to RAM for maximum performance. For data access: Burst reads achieve maximum throughput. Sequential access is faster than random access. The read speed is comparable to competing NOR Flash products and sufficient for most embedded applications.

Up to 50MHz standard, 80MHz dual/quad. Contact our FAE team for high-speed read optimization.