GJGD1201S

The GJGD1201S provides +18V output voltage instead of the +15V used for IGBTs because SiC MOSFETs require higher gate voltage for optimal enhancement. While SiC MOSFETs can operate with +15V gate drive, they typically achieve their specified RDS(on) at +18V to +20V. At +15V, the device may not be fully enhanced, resulting in higher conduction losses. The +18V output ensures the SiC MOSFET operates at its optimal point, minimizing RDS(on) and conduction losses. This is particularly important in high-efficiency applications like EV traction inverters where every fraction of a percent efficiency matters. The -3V negative turn-off voltage provides adequate noise immunity for SiC's lower threshold voltage (typically 2.5-3.5V) compared to IGBTs (typically 5-6V). The +18V/-3V combination provides optimal performance for SiC MOSFETs while maintaining safe operating margins.

Use +18V for optimal SiC MOSFET performance. +15V is acceptable but results in slightly higher losses. Contact our FAE team for gate voltage optimization.

The GJGD1201S features an active Miller clamp, which provides enhanced protection compared to the standard Miller clamp in GJGD1201. The standard Miller clamp uses a passive MOSFET that turns on when the gate voltage exceeds approximately 2V during the off state, providing a low-impedance path to sink Miller current. The active Miller clamp in GJGD1201S uses an active detection circuit that responds faster and provides lower impedance than the passive approach. This is particularly important for SiC MOSFETs which have higher dv/dt and lower threshold voltages than IGBTs. The active Miller clamp can sink higher currents and responds more quickly to prevent gate voltage rise. the active Miller clamp in GJGD1201S is optimized for the faster switching characteristics of SiC devices, providing better protection during the critical switching transitions. For high-frequency SiC applications, the active Miller clamp provides essential protection against false turn-on.

Active Miller clamp provides enhanced protection for SiC MOSFETs. Essential for high-frequency SiC applications. Contact our FAE team for Miller clamp design.

Setting the desaturation threshold for SiC MOSFETs with GJGD1201S requires different considerations than for IGBTs. SiC MOSFETs have different on-state characteristics - instead of a relatively constant VCE(sat) like IGBTs, SiC MOSFETs have a resistive characteristic where VDS = ID × RDS(on). The desaturation threshold should be set above the maximum expected VDS during normal operation. For example, with a SiC MOSFET having 40mΩ RDS(on) and maximum current of 60A, the maximum VDS would be 60A × 0.04Ω = 2.4V. The desaturation threshold should be set well above this, typically at 6-9V. The GJGD1201S allows threshold adjustment through external resistor dividers. The blanking time should also be optimized - SiC MOSFETs switch faster than IGBTs, so shorter blanking times can be used. However, the blanking time must still be sufficient to avoid false triggering during normal switching. Gejian provides application notes for desaturation threshold calculation for SiC MOSFETs.

Set desat threshold above max VDS (ID × RDS(on)). Use 6-9V typical for SiC MOSFETs. Contact our FAE team for desat threshold calculation.

Proper PCB layout is critical for reliable operation of GJGD1201S with SiC MOSFETs due to the high switching speeds involved. Key layout considerations include: Minimize the gate drive loop inductance by placing the driver close to the SiC MOSFET gate and Kelvin source pins. Use wide, short traces for gate drive connections. Place decoupling capacitors (100nF ceramic plus 10-47μF electrolytic) as close as possible to the driver supply pins. Use a Kelvin connection for the gate drive ground - connect the driver's ground return to the Kelvin source pin, not the power source connection. Separate the power ground and control ground, connecting them at a single point to prevent ground bounce. Use proper isolation techniques - maintain adequate creepage and clearance distances for the reinforced isolation barrier. Shield sensitive control signals from the high dv/dt switching nodes. Use proper termination for high-speed digital signals to the driver. Gejian provides reference layouts and layout guidelines for optimal performance.

Minimize gate loop inductance, use Kelvin source connection, place decoupling caps close to driver. Contact our FAE team for layout review.

Yes, the GJGD1201S can be used with parallel SiC MOSFET configurations, though careful design is required. For parallel SiC MOSFETs, each device should have its own gate resistor (typically 2-5Ω) to prevent oscillations between devices. A single GJGD1201S can drive up to 2-3 parallel SiC MOSFETs if they are co-located and the gate drive loop inductance is minimized. For larger parallel configurations, consider using multiple GJGD1201S drivers with synchronized inputs. The Kelvin source connection becomes even more important with parallel devices - each device should have its own Kelvin source connection to the common gate drive ground. Symmetrical layout is critical to ensure balanced switching of parallel devices. The active Miller clamp in GJGD1201S helps prevent false turn-on that could cause shoot-through in parallel configurations. For high-power applications with many parallel devices, consider using a gate drive transformer with multiple secondary windings to provide isolated gate drives for each device.

Use individual gate resistors for each parallel device. Ensure symmetrical layout and Kelvin source connections. Contact our FAE team for parallel SiC design.

The GJGD1201S can support switching frequencies up to 500kHz, though practical maximum frequencies depend on the SiC MOSFET and application requirements. The driver's 6A peak current and fast propagation delay (typically 50-80ns) enable high-frequency operation. However, at very high frequencies, gate drive power dissipation becomes significant. Gate drive power can be calculated as P = Qg × Vgs × fsw, where Qg is total gate charge, Vgs is gate voltage swing, and fsw is switching frequency. For a SiC MOSFET with 80nC gate charge and +18V/-3V drive (21V swing), gate drive power at 100kHz is 80nC × 21V × 100kHz = 168mW. At 500kHz, this increases to 840mW. The driver's thermal design must accommodate this power dissipation. For most practical SiC applications, switching frequencies of 50-200kHz provide good balance between magnetic component size and gate drive losses. The GJGD1201S propagation delay remains consistent across the frequency range, ensuring reliable operation.

GJGD1201S supports up to 500kHz. Consider gate drive power dissipation at high frequencies. Contact our FAE team for high-frequency design.