Crystal Oscillator PCB Layout Guidelines

Proper PCB layout is critical for reliable crystal oscillator operation. This guide covers best practices for laying out crystal circuits on PCBs.

Trace Routing Guidelines

Keep Traces Short

• Minimize crystal-to-MCU trace length
• Target: less than 10mm (0.4 inches) if possible
• Long traces increase stray capacitance and noise pickup

Symmetric Layout

• Keep C1 and C2 traces equal length
• Maintain symmetry around crystal
• Prevents unbalanced loading and frequency offset

No Vias on Crystal Traces

• Avoid vias between crystal and MCU
• Vias add inductance and impedance discontinuities
• Route directly on same layer if possible

Grounding

Solid Ground Plane

• Use continuous ground plane under crystal circuit
• Ground plane reduces noise and provides shielding
• Avoid splitting ground plane under crystal

Ground Vias

• Place ground vias near load capacitors
• Connect capacitor ground to solid ground plane
• Minimize ground loop area

Guard Ring (Optional)

• For noisy environments, add grounded guard ring
• Place around crystal and traces
• Connect to ground at multiple points

Noise Isolation

Keep Away from Noise Sources

• Route away from switching power supplies
• Avoid proximity to high-speed digital signals
• Keep away from RF circuits and antennas
• Maintain 3-5mm clearance from noisy traces

Shielding

• Consider ground pour around crystal circuit
• Use via stitching for shielding effectiveness
• Critical for high-precision applications

Component Placement

Crystal Placement

• Place crystal close to MCU oscillator pins
• Orient to minimize trace length
• Avoid placement near board edges (vibration)

Load Capacitor Placement

• Place C1 and C2 close to crystal pads
• Connect directly to crystal and ground
• Minimize trace length to ground

Series Resistor (if used)

• Place close to MCU output pin
• Typical value: 100Ω to 1kΩ
• Helps limit drive level and reduce EMI