PGT180H
High-performance SoC FPGA with 180K logic elements, dual-core ARM, and 12.5Gbps transceivers for communications.
Product Overview
Description
The PGT180H is Unisplendour's flagship SoC FPGA, combining programmable logic with dual-core ARM Cortex-A9 processors.
With 180,000 logic elements, 800 DSP blocks, and 16 high-speed transceivers supporting up to 12.5Gbps, it addresses demanding applications in 5G communications and high-performance computing.
The integrated hard processor system runs Linux and provides high-bandwidth connectivity to the programmable fabric through AXI interfaces.
Product Series
PGT
Primary Application
5G baseband processing
Key Features
- Dual-core ARM Cortex-A9 processor
- 180K programmable logic elements
- 16 high-speed transceivers (12.5Gbps)
- 800 high-performance DSP blocks
- PCIe Gen3 x8 hard IP
- DDR3/DDR4 memory controller
Specifications
| Logic Elements | 180,000 |
|---|---|
| DSP Blocks | 800 (18x25 multipliers) |
| Memory | 13.5 Mbit embedded RAM |
| Transceivers | 16 channels @ 12.5 Gbps |
| Processor | Dual-core ARM Cortex-A9 @ 800MHz |
| I/O Pins | 896 (up to 36 banks) |
Applications
5G baseband processing
Electronic system design
Optical transport networks
Communication and interface
High-performance computing
Electronic system design
Video processing
Electronic system design
Network acceleration
Communication and interface
FAE Expert Insights
"The PGT180H is Unisplendour's entry into the high-performance FPGA market, competing directly with Xilinx Zynq and Intel Arria. I've worked with customers deploying this device in 5G base stations and optical transport equipment. The integration of dual-core ARM processors with high-performance programmable fabric enables complete system-on-chip solutions. The 12.5Gbps transceivers handle CPRI and Ethernet protocols reliably. Power consumption is competitive with international alternatives. Development using Pango Design Suite has improved significantly - the tool flow is now mature enough for production designs. For customers looking for domestic FPGA solutions with high performance, the PGT180H is a compelling option."
High-performance SoC FPGA with competitive features
— Dr. Wei Zhang, BeiLuo
Frequently Asked Questions
What is the maximum data rate for PGT180H transceivers?
The PGT180H features 16 high-speed transceivers supporting data rates from 614 Mbps to 12.5 Gbps per channel. These transceivers support various protocols including PCIe Gen3, 10G Ethernet, CPRI, Interlaken, and SATA. The transceivers include programmable equalization and pre-emphasis to compensate for channel losses. For 5G fronthaul applications, the 9.8Gbps CPRI rate is fully supported. The transceivers are compatible with standard SFP+ and XFP optical modules.
Verify protocol requirements against transceiver specifications. Contact FAE for signal integrity analysis.
How does the ARM processor connect to the FPGA fabric?
The dual-core ARM Cortex-A9 processors connect to the programmable fabric through multiple high-bandwidth AXI interfaces: AXI bus matrix provides non-blocking connectivity between processors and FPGA logic. Accelerator Coherency Port (ACP) allows FPGA logic to access processor cache. Multiple AXI master and slave ports support various data flow patterns. Maximum theoretical bandwidth exceeds 100 Gbps between processor and fabric. This architecture enables tight integration of software and hardware processing.
Use ACP for cache-coherent data sharing. Use AXI masters for high-throughput data movement.
What is the power consumption of PGT180H?
PGT180H power consumption depends on utilization and activity: Static power (device idle): 2-3W. Typical dynamic power: 5-8W for moderate utilization. Maximum power (fully utilized): 15-20W. Power breakdown: Programmable logic (40-50%), Transceivers (30-40%), Processor system (10-20%). Pango Design Suite provides power estimation based on actual design. Thermal management required for designs >10W. Recommended: heatsink with airflow for typical applications.
Use PDS power estimator. Plan thermal management for >10W designs.
What memory interfaces does PGT180H support?
PGT180H supports various memory interfaces through hard and soft controllers: DDR3/DDR3L up to 1866 Mbps (hard controller). DDR4 up to 2400 Mbps (hard controller). LPDDR3 for low-power applications. QSPI flash for boot and storage. Parallel NOR flash. The hard memory controllers support up to 72-bit wide interfaces with ECC. Maximum memory bandwidth exceeds 25 GB/s with dual-channel DDR4. Soft controllers can be implemented in fabric for specialized memory types.
Use hard DDR4 controller for maximum performance. Use QSPI for cost-sensitive boot storage.
What is the development flow for PGT180H?
PGT180H development follows standard FPGA design flow: Design entry using VHDL, Verilog, or schematic in Pango Design Suite. Functional simulation using ModelSim or integrated simulator. Synthesis targeting PGT180H architecture. Place and route with timing optimization. Static timing analysis to verify performance. Bitstream generation for configuration. Programming via JTAG or SPI flash. For SoC designs, software development using ARM DS-5 or GCC toolchain. Linux BSP available for processor subsystem.
Use Pango Design Suite for complete flow. Contact BeiLuo for software licensing.
Is PGT180H suitable for 5G base station applications?
Yes, PGT180H is well-suited for 5G base station applications: 12.5Gbps transceivers support eCPRI/CPRI front haul interfaces. Sufficient DSP blocks for massive MIMO precoding. Dual-core ARM processors for L2/L3 processing. High-speed memory interfaces for data buffering. PCIe Gen3 for accelerator cards. Multiple devices deployed in 5G small cell and macro base stations in China. Reference designs available for common 5G baseband functions.
Evaluate against specific 3GPP requirements. Contact FAE for 5G reference designs.