Getting Started with UNISOC FPGA Development
Development Environment Setup
Download and install the USC Designer Suite from the UNISOC website. The suite includes synthesis, place-and-route, and simulation tools. System requirements: Windows 10/11, 8GB RAM minimum, 20GB free disk space. After installation, configure the license file and verify the installation by running the included test designs.
Creating Your First Project
Launch USC Designer and create a new project. Select your target device (USC9001 or USC9002) and specify the project directory. Add your Verilog or VHDL source files to the project. Set up the pin assignments using the Pin Planner tool, referencing the device datasheet for available I/O pins and their capabilities.
Synthesis and Implementation
Run synthesis to convert your HDL code into a netlist. Review any warnings or errors in the Messages window. After successful synthesis, run place-and-route to map the design to the FPGA resources. Check the utilization report to verify resource usage. Generate the programming file for device configuration.
Device Programming
Connect the USB programmer to your development board and PC. Open the Programmer tool in USC Designer and load the generated programming file. Select the appropriate programming mode (JTAG or Active Serial). Click Program to configure the FPGA. Verify successful configuration by observing the on-board LEDs or using SignalTap logic analyzer.
💡 FAE Insights
📋 Customer Cases
Challenge
Team was new to UNISOC FPGA tools and needed to quickly ramp up development
Solution
Followed the getting started guide and example designs, completed first working design in one week
Results
Development team became productive quickly, first prototype successful on second iteration
Frequently Asked Questions
1. What programming languages are supported?
USC Designer supports both Verilog (IEEE 1364) and VHDL (IEEE 1076) languages. SystemVerilog is partially supported for synthesis. For detailed specifications and application support on unisoc products, refer to the datasheet or contact our team.
2. Can I import designs from Xilinx or Intel tools?
HDL source code can be imported directly. However, vendor-specific IP cores and constraints will need to be adapted for UNISOC architecture. For detailed specifications and application support on unisoc products, refer to the datasheet or contact our team.
3. Is there a free license available?
Yes, a free license is available for evaluation and small designs. The free license has limitations on device size and features. For detailed specifications and application support on unisoc products, refer to the datasheet or contact our team.
4. What simulation tool is included?
USC Designer includes an integrated simulator based on ModelSim technology. It supports both functional and timing simulation. For detailed specifications and application support on unisoc products, refer to the datasheet or contact our team.
5. How do I debug my FPGA design?
Use the integrated SignalTap logic analyzer for real-time debugging. It allows probing internal signals without additional hardware. For detailed specifications and application support on unisoc products, refer to the datasheet or contact our team.