NOR Flash Memory Selection Guide
NOR Flash memory is the preferred choice for code storage and execute-in-place (XIP) applications due to its fast random read access. This guide covers key selection criteria for NOR Flash products. Density selection should consider current code size plus 50% margin for future growth. Common densities range from 16Mb to 256Mb for embedded applications. Interface selection affects both performance and design complexity. Standard SPI is simplest but slowest. Dual and Quad SPI offer 2x and 4x performance improvement. Parallel interface provides maximum performance but requires more pins. Speed requirements depend on boot time targets and code execution performance. QSPI at 133MHz can achieve 60+ MB/s throughput. Consider voltage compatibility with your MCU and operating temperature range for your application environment.
💡 FAE Insights
⚠️ Common Pitfalls
- ✗ Undersizing density
- ✗ Ignoring interface capabilities
- ✗ Missing temperature requirements
📋 Customer Cases
Embedded Systems Manufacturer
Industrial Automation
Challenge
Needed fast boot time for industrial IoT gateway with limited RAM.
Solution
Upgraded to QSPI NOR Flash with XIP configuration, optimized boot sequence.
Customer Feedback
"Following the selection guide helped us choose the optimal NOR Flash with QSPI interface, reducing boot time by 60%."
Results
Boot time reduced to 800ms, meeting customer requirements. RAM requirements reduced by 50%.
Frequently Asked Questions
1. How do I calculate NOR Flash read performance?
NOR Flash read performance depends on interface type and clock frequency. Standard SPI: 1 bit per clock. Dual SPI: 2 bits per clock. Quad SPI: 4 bits per clock. At 133MHz: Standard SPI = 16.6 MB/s, Dual SPI = 33.3 MB/s, Quad SPI = 66.6 MB/s. Actual throughput is slightly lower due to command and address overhead. For continuous reads, effective throughput is typically 80-90% of theoretical maximum.
2. What is execute-in-place (XIP) and when should I use it?
Execute-in-place allows the MCU to run code directly from NOR Flash without copying to RAM. Benefits include reduced RAM requirements and faster boot time. Drawbacks include slower execution speed compared to RAM and higher power consumption. XIP is suitable for: 1) Systems with limited RAM. 2) Applications where code fits in cache. 3) Boot code and initialization. 4) Infrequently executed code. Copy to RAM is better for performance-critical code that runs frequently.
3. How do I determine the required NOR Flash density?
Calculate required density by: 1) Sum current code size (bootloader + application + data). 2) Add 50% margin for future growth and updates. 3) Add space for configuration data and logs. 4) Round up to next standard density (16Mb, 32Mb, 64Mb, 128Mb, 256Mb). Example: 6MB code + 3MB margin = 9MB -> select 128Mb (16MB). Consider dual-bank requirements for firmware updates.
4. What security features should I consider?
Important security features include: 1) Hardware write protection - WP pin for boot sector protection. 2) Software write protection - configuration registers for flexible protection. 3) OTP regions - one-time programmable for unique IDs and keys. 4) Block protection - individual block locking. 5) Security registers - for device authentication. These features protect against unauthorized modification and enable secure boot.
5. How do I interface NOR Flash with my MCU?
NOR Flash interfacing depends on interface type: For SPI: Connect CS, CLK, MOSI, MISO pins. Add pull-ups on CS and WP. Use SPI controller in MCU. For QSPI: Connect additional IO2, IO3 pins. Configure MCU for QSPI mode. For Parallel: Connect address, data, and control buses. Use external latch if needed. Ensure voltage levels match between Flash and MCU. Check timing requirements against MCU specifications.