UN25N128
128Mb SPI NOR Flash with 133MHz clock, supporting fast read and dual/quad SPI modes for embedded applications.
Product Overview
Description
The UN25N128 provides 128Mb (16MB) of non-volatile storage in a compact 8-pin package. With SPI interface supporting up to 133MHz clock and dual/quad read modes, it delivers fast code execution for embedded systems.
The device features uniform 4KB sector erase, 32KB/64KB block erase, and page program capabilities. Advanced security features include software and hardware write protection, allowing secure boot code storage.
Low-power operation modes including deep power-down make it ideal for battery-powered applications. The device operates from a single 2.7V to 3.6V supply and is available in industrial and automotive temperature grades.
Product Series
UN
Primary Application
Boot code storage
Key Features
- 128Mb density
- 133MHz SPI
- Quad I/O
- Hardware protection
- Low power
Specifications
| Density | 128Mb (16MB) |
|---|---|
| Interface | SPI (Single/Dual/Quad) |
| Clock Rate | Up to 133MHz |
| Read Speed | Up to 66MB/s (Quad mode) |
| Supply Voltage | 2.7V to 3.6V |
| Operating Temperature | -40C to +85C (Industrial), -40C to +125C (Automotive) |
| Package | SOP-8, WSON-8, USON-8 |
Applications
Boot code storage
Electronic system design
Firmware
Electronic system design
Embedded systems
Electronic system design
IoT devices
Electronic system design
Automotive
Automotive and EV electronics
FAE Expert Insights
"I highly recommend the UN25N128 for embedded boot applications. In my experience supporting numerous industrial designs, this NOR Flash delivers consistent performance. The 133MHz SPI interface provides excellent boot times, and I have found the quad mode particularly effective for reducing system startup time by up to 60%. The write protection features are robust - I always recommend using the hardware WP pin for boot sector protection in security-sensitive applications. The industrial temperature grade is genuine and reliable. For battery-powered IoT devices, the deep power-down mode is essential. I believe this product offers the best value in its class for cost-sensitive embedded designs."
Reliable NOR Flash with fast 133MHz SPI and quad mode support
— Li Wei, BeiLuo
Frequently Asked Questions
How do I calculate read performance in quad mode?
In quad mode, 4 bits are transferred per clock cycle. At 133MHz, theoretical peak throughput is 133M x 4 = 532Mbps = 66.5MB/s. Actual throughput is slightly lower due to command overhead and address cycles. For continuous reads, expect 60-65MB/s effective throughput. This is 4x faster than standard SPI mode. The MCU must support QSPI interface to utilize this mode.
Verify your MCU supports QSPI for maximum performance. Contact us for interface compatibility verification.
What is the sector erase time?
Typical sector erase (4KB) time is 50-200ms depending on conditions. Block erase (32KB/64KB) is proportionally faster per byte. Full chip erase takes longer proportionally. Erase time increases at lower temperatures and over device lifetime. For applications requiring fast updates, consider the 32KB block size option. The device supports suspend/resume for interrupting long erase operations.
Plan erase operations during idle periods. Use block erase for bulk updates.
What is the power consumption in different modes?
Active read current: 15-25mA at 133MHz. Program current: 20-30mA. Erase current: 25-35mA. Standby current: 50-100uA. Deep power-down: 5-10uA. Power consumption depends on voltage, temperature, and clock frequency. Lower clock speeds reduce active power. Deep power-down mode is recommended for battery-powered applications during idle periods.
Use deep power-down mode for battery applications. Contact us for power analysis tools.
How many write cycles can this device handle?
The UN25N128 is rated for minimum 100,000 program/erase cycles per sector. With proper wear leveling, the device can support millions of write operations across the entire array. For applications with high write frequency, implement wear leveling in software to distribute writes evenly. The device includes status registers to monitor block health. At end of life, blocks become read-only rather than failing completely.
Implement wear leveling for high-write applications. Monitor block status registers.
What is the data retention specification?
Data retention is specified as 20 years minimum after programming. Retention decreases with increasing temperature and number of write cycles. At 55C after 100K cycles, retention is typically 10 years. For long-term storage applications, avoid frequent rewriting and maintain moderate operating temperatures. The device includes read disturb protection for frequently accessed sectors.
For archival storage, minimize rewrites and maintain moderate temperatures.