Power Supply Design for Runic Analog Circuits
Clean power supplies are essential for achieving the specified performance of precision analog circuits. This guide covers power supply design considerations for Runic op-amps, ADCs, and voltage references.
Power Supply Requirements
Precision analog circuits require power supplies with:
- Low noise: <10μVrms for high-resolution ADCs
- High PSRR: >60dB at operating frequencies
- Good load regulation: <1% for dynamic loads
- Stable output: <0.1% variation over temperature
LDO Selection
For analog circuits, select LDOs with:
- Low output noise: <20μVrms (10Hz-100kHz)
- High PSRR: >60dB at 1kHz, >40dB at 100kHz
- Fast transient response: <50μs settling
- Low dropout: <200mV at rated current
Recommended Runic LDOs:
- RS7118: Ultra-low noise (10μV), 300mA, for ADC/DAC
- RS7133: Low Iq (25μA), 500mA, for battery apps
- RS7125: General purpose, 500mA, cost-effective
Decoupling Strategy
Effective decoupling requires:
- 100nF ceramic capacitor at each IC power pin
- 10μF bulk capacitor per supply rail
- Place capacitors close to IC (within 2mm)
- Use low-ESR ceramic capacitors (X7R/X5R)
Noise Reduction Techniques
For ultra-low noise applications:
- Use ferrite beads in series with supply
- Add RC filters (10Ω + 10μF) for sensitive circuits
- Implement star grounding
- Separate analog and digital power domains
PCB Layout Guidelines
Power supply layout best practices:
- Use wide traces (min 20mil per amp)
- Minimize loop area for high-frequency currents
- Place LDO close to load
- Use multiple vias for ground connections
💡 FAE Insights
⚠️ Common Pitfalls
- ✗ Inadequate decoupling capacitor placement
- ✗ Using switching regulators without filtering
- ✗ Sharing analog and digital supplies
- ✗ Ignoring PSRR at high frequencies
- ✗ Not measuring actual noise levels
Frequently Asked Questions
1. What LDO should I use for powering precision ADCs?
For precision ADCs, I recommend the RS7118 ultra-low-noise LDO. Key specs: (1) 10μVrms noise - critical for maintaining ADC SNR; (2) 80dB PSRR at 1kHz - rejects supply ripple; (3) 300mA current - sufficient for ADC plus reference; (4) Fast transient response - handles ADC sampling current spikes. Place the LDO close to the ADC (within 10mm) with 100nF ceramic capacitor at the ADC power pin. Add a 10μF bulk capacitor at the LDO output. For multi-channel ADCs, consider individual LDOs per channel to prevent crosstalk.
2. How do I calculate the noise impact on my ADC?
To calculate power supply noise impact on ADC: (1) Determine ADC PSRR from datasheet (typically 60-80dB); (2) Measure supply noise with spectrum analyzer (Vnoise); (3) Calculate referred noise: Vreferred = Vnoise / 10^(PSRR/20); (4) Compare to ADC LSB: LSB = Vref / 2^N; (5) Noise should be <0.5 LSB for negligible impact. Example: 16-bit ADC with 5V ref, LSB = 76μV. With 80dB PSRR and 10mV noise: Vreferred = 10mV / 10^4 = 1μV. This is << 0.5 LSB (38μV), so impact is negligible. If noise is higher, add filtering or select better LDO.
3. Should I use separate supplies for analog and digital circuits?
Yes, separate analog and digital supplies are strongly recommended for mixed-signal designs. Digital switching creates noise on the supply that can couple into analog circuits. Implementation: (1) Use separate LDOs for analog and digital; (2) Connect grounds at a single point (star ground); (3) Add ferrite beads between supplies for isolation; (4) Keep analog and digital return currents separate. For cost-sensitive designs, a single LDO with separate RC filters for analog sections can work, but performance may be compromised. The RS7118 for analog and RS7133 for digital is a good combination.