CBM94AD67
High-performance 14-bit ADC with 250MSPS sampling rate, 72dB SNR, and LVDS output for communications and instrumentat...
Product Overview
Description
The CBM94AD67 is a high-performance 14-bit analog-to-digital converter designed for demanding communications and instrumentation applications. It features a pipelined architecture achieving 250MSPS sampling rate with excellent dynamic performance.
With 72dB SNR and 85dBc SFDR, the CBM94AD67 delivers high-fidelity signal conversion for wideband receivers and transmitters. The differential input accepts 1.5Vpp signals with flexible common-mode voltage.
The ADC provides LVDS digital outputs and SPI configuration interface. Operating from 1.8V and 3.3V supplies, it consumes only 380mW typical power. The device is available in a compact 7x7mm QFN package.
Product Series
CBM
Primary Application
4G/5G base station receivers
Key Features
- High 250MSPS sampling rate
- Excellent 72dB SNR performance
- Low 380mW power consumption
- Flexible 1.5Vpp differential input
- LVDS digital outputs
- SPI configuration interface
- Compact 7x7mm QFN package
- Industrial temperature range
Specifications
| Resolution | 14-bit |
|---|---|
| Sampling Rate | 250 MSPS |
| SNR | 72 dBFS @ 70MHz |
| SFDR | 85 dBc @ 70MHz |
| ENOB | 11.8 bits |
| Power Consumption | 380 mW |
| Input Range | 1.5Vpp differential |
| Interface | LVDS / SPI |
| Package | 7x7mm QFN-48 |
Applications
4G/5G base station receivers
Electronic system design
Wideband communications
Communication and interface
Software-defined radio
Electronic system design
Radar and electronic warfare
Electronic system design
Medical imaging
Medical electronics
Test and measurement
Data acquisition and conversion
FAE Expert Insights
"The CBM94AD67 is an excellent ADC that I've successfully deployed in multiple communication systems. In my experience, the 72dB SNR and 85dBc SFDR are competitive with international brands at a much better price point. I particularly appreciate the flexible input configuration which simplifies front-end design. The LVDS outputs integrate well with FPGA-based systems. One key recommendation: pay close attention to clock jitter as it directly impacts SNR performance. With a clean clock source, customers can achieve the full 72dB SNR specification. The 380mW power consumption is reasonable for this performance class. For cost-sensitive communication designs, this ADC offers excellent value."
High-performance ADC ideal for communications with excellent price-performance ratio
— Michael Chen, BeiLuo
Frequently Asked Questions
What is the typical power consumption of CBM94AD67?
The CBM94AD67 typical power consumption is 380mW at 250MSPS sampling rate with all digital outputs active. Power consumption scales with sampling rate: approximately 300mW at 125MSPS and 380mW at 250MSPS. The device supports power-down modes reducing consumption to <10mW when disabled. For power-sensitive applications, consider disabling unused digital outputs and using lower sampling rates when possible. The 1.8V digital supply can be reduced to save additional power in some applications.
Expect 380mW typical at full speed; use power-down modes for battery applications.
What is the input bandwidth of CBM94AD67?
The CBM94AD67 features a wide analog input bandwidth of 650MHz (-3dB), enabling direct RF sampling applications. The full-power bandwidth supports input frequencies up to 300MHz while maintaining rated SNR performance. For undersampling applications, the device can sample signals well above Nyquist. The differential input structure provides excellent common-mode rejection. Input impedance is approximately 4kΩ differential in parallel with 2pF. For wideband applications, use appropriate anti-aliasing filters and termination.
650MHz bandwidth supports direct RF sampling; use anti-aliasing filters for best performance.
How do I configure CBM94AD67 registers?
The CBM94AD67 is configured through a 3-wire SPI interface: (1) CS - chip select, active low; (2) SCLK - serial clock, up to 20MHz; (3) SDIO - serial data input/output. Configuration steps: (1) Assert CS low; (2) Send 16-bit command (7-bit address + 9-bit data); (3) Deassert CS high. Key registers include: 0x00 - chip configuration, 0x01 - clock divider, 0x02 - output mode, 0x03 - test patterns. The device powers up with default settings suitable for most applications. Detailed register map is provided in the datasheet.
Use SPI interface for configuration; default settings work for most applications.
What output formats does CBM94AD67 support?
The CBM94AD67 supports multiple output formats: (1) Offset binary - unipolar coding from 0 to 16383; (2) Two's complement - bipolar coding from -8192 to +8191; (3) Gray code - for special applications. The default is offset binary. Output mode is configured via SPI register 0x02. The LVDS outputs operate at 250MSPS x 14 bits = 3.5Gbps total data rate. The device supports double-data-rate (DDR) LVDS to reduce pin count. Output timing is adjustable via register settings to match FPGA capture.
Use offset binary for unipolar, two's complement for bipolar applications.
Does CBM94AD67 support multi-chip synchronization?
Yes, the CBM94AD67 supports multi-chip synchronization for phased array and MIMO applications: (1) SYNC input - external synchronization signal aligns internal clocks; (2) SYSREF input - JESD204B-style reference for deterministic latency; (3) Clock distribution - use same clock source for all ADCs; (4) Digital reset - synchronous reset ensures aligned data output. For precise phase matching, use matched PCB traces for clock and analog inputs. The device-to-device phase mismatch is typically <100ps. Contact LiTong FAE for multi-chip synchronization design support.
Use SYNC and SYSREF inputs for multi-chip synchronization in array applications.