ISL80103
High-performance 3A LDO with ultra-low noise and high PSRR for sensitive analog and RF applications.
Product Overview
Description
The ISL80103 is a high-performance 3A low-dropout (LDO) linear regulator featuring ultra-low output noise and high power supply rejection ratio (PSRR).
With only 40µVrms output noise from 10Hz to 100kHz and 70dB PSRR at 1kHz, it provides clean power for sensitive analog circuits, RF transceivers, and high-speed data converters.
The device operates from 2.2V to 6V input and offers adjustable output from 0.8V to 5V, making it ideal for post-regulation in noise-sensitive applications.
Product Series
ISL
Primary Application
RF power supplies
Key Features
- Ultra-low output noise 40µVrms
- High PSRR 70dB at 1kHz
- 3A continuous output current
- Low dropout voltage 180mV at 3A
- Wide input voltage range 2.2V-6V
- Adjustable output 0.8V-5V
- Excellent load/line regulation
- Thermal shutdown protection
Specifications
| Input Voltage | 2.2V to 6V |
|---|---|
| Output Voltage | 0.8V to 5V adjustable |
| Output Current | 3A |
| Dropout Voltage | 180mV at 3A |
| PSRR | 70dB at 1kHz |
| Output Noise | 40µVrms (10Hz-100kHz) |
| Package | DFN-10, TQFN-10 |
Applications
RF power supplies
Electronic system design
ADC/DAC reference
Data acquisition and conversion
Clock and PLL power
Electronic system design
Medical imaging
Medical electronics
Test equipment
Electronic system design
FAE Expert Insights
"The ISL80103 is my go-to LDO for noise-sensitive applications. The 40µVrms noise figure is exceptional - I've used this LDO to power high-resolution ADCs where every microvolt of noise matters. The high PSRR effectively rejects switching noise from upstream DC-DC converters. The 3A capacity handles most analog power requirements without needing parallel devices. The small DFN package is convenient for space-constrained designs. For sensitive analog circuits, this LDO delivers performance comparable to much more expensive discrete solutions."
Ultra-low noise for sensitive analog applications
— Michael Chen, BeiLuo
Frequently Asked Questions
How do I minimize output noise from ISL80103?
To achieve minimum output noise: Use a 10µF or larger ceramic output capacitor with X7R dielectric; Add a small 0.01µF bypass capacitor close to the load; Keep input capacitor close to the LDO; Minimize ground loop area; Use thick traces for output to reduce resistance. For the lowest noise, add a noise reduction capacitor (CNR) between BYP pin and ground - typical value 10nF.
Use quality ceramic capacitors and follow layout best practices. Contact us for noise-sensitive design guidance.