Designing hardware with Loongson processors requires attention to power delivery, high-speed interfaces, and thermal management. This guide provides practical guidelines for successful hardware design.

Power Delivery Design

Proper power delivery is critical for reliable operation.

3A5000 Power Requirements

RailVoltageCurrent (Max)Tolerance
VDD_CPU0.9V40A+/- 50mV
VDD_DDR1.2V10A+/- 60mV
VDD_SOC1.0V5A+/- 50mV
VDD_IO1.8V/3.3V3A+/- 100mV

Power Design Best Practices

  • Use multi-phase VRM for CPU core: 4+ phases recommended for 3A5000
  • Implement load-line regulation: Compensate for IR drop under load
  • Provide adequate bulk capacitance: 1000uF+ near VRM output
  • Use sufficient decoupling: Follow reference design for capacitor placement
  • Monitor power rails: Include test points for debugging
  • Power Sequencing

    Follow proper power-up sequence:

  • VDD_IO (1.8V/3.3V) - First
  • VDD_DDR (1.2V) - Second
  • VDD_SOC (1.0V) - Third
  • VDD_CPU (0.9V) - Last
  • Power-down is reverse order. Use dedicated power sequencer IC or implement in CPLD.

    DDR Memory Interface

    DDR4 interface requires careful design for signal integrity.

    DDR4 Routing Guidelines

    ParameterSpecification
    Trace impedance40 Ohm single-ended, 80 Ohm differential
    Trace length match+/- 2mm within byte lane
    Clock to DQ skew< 100ps
    Via countMinimize, max 2 per net
    LayerRoute on internal stripline layers

    DDR4 Layout Recommendations

  • Place memory close to processor: Keep traces under 3 inches
  • Route on single layer per byte lane: Avoid layer changes
  • Match trace lengths carefully: Use serpentine routing if needed
  • Provide solid ground reference: No splits under DDR traces
  • Use adequate decoupling: 100nF per power pin minimum
  • DDR4 Topology

    Loongson 3A5000 supports dual-channel DDR4. Each channel is point-to-point:

    ``

    CPU DDR Controller

    |

    |-- Channel 0 --> DIMM0 (64-bit data + ECC)

    |

    |-- Channel 1 --> DIMM1 (64-bit data + ECC)

    ``

    For embedded designs with soldered memory, use x16 or x8 devices to achieve 64-bit width.

    PCIe Interface Design

    PCIe 3.0 requires careful high-speed design.

    PCIe Routing Guidelines

    ParameterPCIe 3.0 Specification
    Trace impedance85 Ohm differential
    Trace length< 8 inches for x16
    Lane-to-lane skew< 3ps
    AC coupling100nF caps near receiver
    Via styleUse back-drill or blind vias

    PCIe Layout Best Practices

  • Route on outer layers when possible: Better impedance control
  • Avoid vias in high-speed section: Each via adds discontinuity
  • Provide clean reference plane: No plane splits under traces
  • Match pair lengths: Within 5 mils for each differential pair
  • Space from other signals: 3W spacing from aggressor signals
  • PCIe Clocking

    • Use 100MHz differential reference clock
    • Route clock with data lanes (separate pair)
    • Match clock length to data length
    • Use spread spectrum clocking if supported

    Ethernet Interface Design

    Gigabit Ethernet requires proper magnetics and termination.

    Ethernet Magnetics Selection

    Key parameters:

    • Turns ratio: 1:1 for voltage mode PHYs
    • Insertion loss: < 1.0dB at 100MHz
    • Return loss: > 16dB at 100MHz
    • Crosstalk: > 40dB
    • Isolation: 1500V minimum

    Ethernet Layout Guidelines

  • Place magnetics close to connector: Minimize unshielded traces
  • Route as differential pairs: 100 Ohm differential impedance
  • Keep traces short: Under 1 inch from PHY to magnetics
  • Provide proper termination: Follow PHY datasheet
  • Implement ESD protection: Place protection devices near connector
  • Thermal Design

    Proper thermal management ensures reliable operation.

    Thermal Requirements

    ProcessorTDPMax JunctionHeatsink Required
    3A500035W105°CYes, active recommended
    3C5000120W105°CYes, active required
    2K10003W105°COptional, passive OK
    2K20005W105°COptional, passive OK

    Heatsink Design

    For active cooling:

  • Select heatsink with adequate thermal mass: Based on TDP
  • Use thermal interface material: 1-2 W/mK minimum
  • Provide airflow: Match fan to heatsink and system impedance
  • Consider heat pipes: For high-TDP processors in compact spaces
  • Mount securely: Even pressure distribution across die
  • For passive cooling:

  • Use large heatsink: Maximize surface area
  • Ensure natural convection: Adequate venting in chassis
  • Consider chassis as heatsink: Thermal connection to enclosure
  • Validate with thermal testing: Measure actual temperatures
  • Thermal Simulation

    Perform thermal simulation early in design:

    • Model processor as heat source (TDP value)
    • Include heatsink thermal resistance
    • Account for TIM thermal resistance
    • Model airflow (forced or natural)
    • Verify junction temperature < 105°C at max ambient

    Signal Integrity

    High-speed signals require careful design.

    General SI Guidelines

  • Control trace impedance: Use PCB stackup calculator
  • Minimize via stubs: Use blind/buried vias or back-drill
  • Provide continuous reference: No plane splits under signals
  • Match trace lengths: Critical for parallel buses and differential pairs
  • Space signals appropriately: 3W rule for single-ended, 5W for differential
  • Stackup Recommendations

    For 6-layer board:

    LayerTypePurpose
    1SignalTop layer, high-speed signals
    2GroundSolid ground plane
    3SignalInternal routing
    4PowerPower distribution
    5GroundSolid ground plane
    6SignalBottom layer, components

    For high-speed designs, consider 8+ layers for better isolation.

    PCB Layout Checklist

    Before manufacturing, verify:

    Power

    • [ ] All power rails present with correct voltage
    • [ ] Adequate copper width for current capacity
    • [ ] Sufficient decoupling capacitors placed
    • [ ] Power sequencing implemented correctly
    • [ ] Test points on all power rails

    DDR Memory

    • [ ] Length matching within specifications
    • [ ] Impedance control verified
    • [ ] Reference planes continuous
    • [ ] Termination resistors correct
    • [ ] Decoupling adequate

    High-Speed Interfaces

    • [ ] PCIe traces length matched
    • [ ] Ethernet magnetics correct
    • [ ] Impedance controlled for all high-speed signals
    • [ ] Via stubs minimized
    • [ ] Crosstalk analyzed

    Thermal

    • [ ] Heatsink mounting provisions
    • [ ] TIM selection appropriate
    • [ ] Airflow path clear
    • [ ] Thermal simulation completed

    Manufacturing

    • [ ] DFM review completed
    • [ ] Test points accessible
    • [ ] Component footprints verified
    • [ ] Silkscreen clear and complete

    Design Validation

    After PCB fabrication:

  • Power-on testing: Verify all power rails
  • Clock verification: Check reference clocks
  • Memory testing: Run memory stress tests
  • Interface testing: Verify PCIe, Ethernet, USB
  • Thermal testing: Measure temperatures under load
  • Stress testing: Run burn-in tests
  • Use oscilloscope to verify:

    • Power rail ripple and noise
    • Clock signal quality
    • High-speed signal eye diagrams

    Reference Designs

    Loongson provides reference designs for:

    • 3A5000 desktop motherboard
    • 2K1000 embedded board
    • 3C5000 server board

    Use these as starting points for custom designs. Reference designs include:

    • Complete schematics
    • PCB layout files
    • BOM with validated components
    • Design documentation

    Getting Help

    For hardware design support:

    • Review reference designs thoroughly
    • Use provided layout guidelines
    • Engage FAE team for design review
    • Consider design services for complex projects

    Proper planning and following guidelines will result in successful hardware design.