LX1632

Calculating multi-channel throughput for the LX1632: The total sampling rate is divided among active channels. Formula: Channel sampling rate = ADC sampling rate / Number of channels. Examples: 8 channels at 100kSPS = 12.5kSPS per channel. 4 channels at 100kSPS = 25kSPS per channel. 2 channels at 100kSPS = 50kSPS per channel. Timing considerations: Channel switching time: ~1μs. Conversion time: ~10μs at 100kSPS. Total cycle time: ~11μs per channel. For 8 channels: 88μs total = 11.36kSPS effective. To maximize throughput: Use auto-scan mode for continuous sampling. Minimize SPI communication overhead. Use burst mode if available. Consider using multiple ADCs for very high channel counts. The LX1632 provides good throughput for most multi-channel applications.

Divide 100kSPS by channel count. Contact our FAE team for multi-channel timing analysis.

The LX1632 supports both single-ended and differential input configurations: Single-ended inputs: Signal measured relative to ground (AGND). 8 channels available (AIN0-AIN7). Simpler wiring and interface. More susceptible to ground noise. Suitable when: Ground is clean and stable. Cost and simplicity are priorities. Signal source is ground-referenced. Differential inputs: Signal measured between two inputs (AIN+ and AIN-). 4 channel pairs available. Rejects common-mode noise. Better noise immunity. Suitable when: Ground noise is present. Long cable runs are needed. High noise immunity required. The LX1632 can be configured for either mode via control register. Differential mode provides better performance in noisy environments but requires more wiring. For best performance in industrial environments, differential inputs are recommended.

Use differential for noisy environments, single-ended for simple wiring. Contact our FAE team for input configuration.

The LX1632 auto-scan mode automatically sequences through selected channels: Configuration steps: Select channels to scan via CHSEL register. Set scan mode bit in control register. Set sampling rate. Start conversion. Operation: ADC automatically switches to next channel after each conversion. DRDY signals when each conversion is complete. Read data via SPI. Sequence repeats continuously. Benefits: Reduces MCU overhead - no need to change channels manually. Ensures consistent timing between channels. Simplifies software design. Example sequence for channels 0-3: Configure CHSEL = 0x0F (channels 0-3 enabled). Set SCAN = 1. Start conversions. DRDY goes low when CH0 data ready. Read CH0 data. DRDY goes low when CH1 data ready. Read CH1 data. Repeat for CH2, CH3, then back to CH0. The auto-scan mode is ideal for data acquisition systems requiring regular sampling of multiple channels.

Use auto-scan for continuous multi-channel sampling. Contact our FAE team for scan mode configuration.

The LX1632 power consumption scales with sampling rate: Power specifications: 100kSPS: ~10mW (3.3V supply, ~3mA). 50kSPS: ~6mW (~1.8mA). 10kSPS: ~2mW (~0.6mA). Power-down mode: ~10μW (~3μA). Power saving strategies: Use power-down between conversions for low duty cycle. Reduce sampling rate if full speed not needed. Disable unused channels. Use external reference only when needed. Power breakdown: Analog front-end: ~40%. ADC core: ~35%. Digital interface: ~25%. For battery-powered applications: Calculate average power based on duty cycle. Consider trade-off between sampling rate and power. Use burst sampling if continuous monitoring not needed. The LX1632 offers good power efficiency for its performance class.

Power scales with sampling rate. Use power-down for low duty cycle. Contact our FAE team for power optimization.

Synchronizing multiple LX1632 ADCs requires careful timing control: Methods for synchronization: Common CONVST signal: Connect CONVST pins of all ADCs together. Drive with single MCU GPIO. All ADCs start conversion simultaneously. SPI readback sequential. Common clock source: Use external clock for all ADCs. Ensures identical sampling instants. Requires external oscillator distribution. Triggered sampling: Use MCU timer to trigger conversions. Software-controlled synchronization. Less precise but simpler. Best practices: Use same reference voltage for all ADCs. Match PCB trace lengths for CONVST and clock. Consider using ADCs with built-in synchronization. For multi-channel systems: Use one LX1632 with 8 channels when possible. Use multiple ADCs only when needed for higher channel count or isolation. The LX1632 does not have dedicated synchronization pins, so external control is needed for precise synchronization.

Use common CONVST for synchronization. Contact our FAE team for multi-ADC system design.

Anti-aliasing filter requirements for the LX1632: Nyquist criterion: Input signals above fs/2 will alias into the passband. For 100kSPS, Nyquist frequency is 50kHz. Filter requirements: Attenuate signals above 50kHz to below 1 LSB. Typical requirement: 60-80dB attenuation at fs/2. Filter options: Single-pole RC: Simple, -20dB/decade. May need high cutoff for adequate attenuation. Multi-pole active filter: Better attenuation, more complex. Switched-capacitor filter: Precise, programmable. Recommended approach: Set filter cutoff at 1/5 to 1/10 of sampling rate (10-20kHz for 100kSPS). Use at least 2-pole filter for 40dB/decade rolloff. Consider input signal bandwidth requirements. Example: 2-pole Butterworth, 10kHz cutoff. Provides 40dB attenuation at 50kHz. Good compromise between bandwidth and aliasing protection. The LX1632 has no internal anti-aliasing filter, so external filtering is required.

Use 2-pole filter with cutoff at 1/5 to 1/10 of sampling rate. Contact our FAE team for filter design.