CG-6OUT-PCIe
Integrated 6-output clock generator for PCIe applications with spread spectrum and low jitter.
Product Overview
Description
This clock generator provides six 100MHz differential outputs meeting PCIe Gen1/Gen2/Gen3 requirements. The integrated PLL provides excellent jitter performance for high-speed serial links.
Spread spectrum capability reduces EMI by 8dB to 12dB, simplifying system EMC compliance. The 25MHz crystal input accepts standard crystals.
The 5.0x5.0mm QFN package integrates all necessary circuitry, reducing BOM count and PCB area compared to discrete solutions.
Product Series
CG
Primary Application
PCIe systems
Key Features
- 6 PCIe clocks
- Spread spectrum
- 0.5ps jitter
- HCSL outputs
Specifications
| Input Frequency | 25MHz crystal |
|---|---|
| Output Frequencies | 6 x 100MHz differential |
| Output Type | HCSL (PCIe compatible) |
| Jitter (RMS) | 0.5ps max (PCIe Gen3 compatible) |
| Spread Spectrum | ±0.5% down-spread, 30kHz modulation |
| Supply Voltage | 3.3V ±5% |
| Operating Temperature | 0C to +70C (commercial), -40C to +85C (industrial) |
| Package | QFN 5.0 x 5.0 x 0.9mm |
Applications
PCIe systems
Electronic system design
Servers
Electronic system design
Workstations
Electronic system design
Embedded systems
Electronic system design
FAE Expert Insights
"The CG-6OUT-PCIe is an excellent choice for PCIe clock distribution. I have used this clock generator in multiple server and workstation designs with great success. The 0.5ps jitter performance easily meets PCIe Gen3 requirements, and I have verified compliance in testing. The spread spectrum feature is valuable for passing EMI testing - I typically see 8-10dB reduction in clock harmonics. The HCSL outputs are directly compatible with PCIe slots and devices. I particularly appreciate the integrated termination resistors which save board space. For systems requiring multiple PCIe clocks, this single device replaces six discrete oscillators, reducing cost and complexity. The 25MHz crystal input accepts standard crystals readily available from our inventory."
Integrated PCIe clock solution with excellent jitter and EMI performance
— Kevin Wu, BeiLuo
Frequently Asked Questions
What PCIe generations does this clock support?
This clock generator supports PCIe Gen1, Gen2, and Gen3: PCIe Gen1 (2.5GT/s) - requires <75ps RMS jitter, this device provides <0.5ps. PCIe Gen2 (5.0GT/s) - requires <3.1ps RMS jitter, this device easily meets. PCIe Gen3 (8.0GT/s) - requires <1.0ps RMS jitter, this device provides <0.5ps. The 100MHz frequency and HCSL output levels meet PCIe specifications. The spread spectrum is PCIe-compliant with 0.5% down-spread. For PCIe Gen4 (16.0GT/s), check specific jitter requirements as they are more stringent. This clock generator is ideal for motherboards, add-in cards, and embedded systems using PCIe.
Compatible with PCIe Gen1/Gen2/Gen3. Contact us for Gen4 requirements.
How do I enable spread spectrum and what are the effects?
Spread spectrum is enabled via the SS_EN pin: Connect SS_EN to VDD - spread spectrum enabled (default). Connect SS_EN to GND - spread spectrum disabled. Effects of spread spectrum: EMI reduction - 8dB to 12dB reduction in clock harmonics. Frequency modulation - clock varies ±0.5% around center frequency at 30kHz rate. System effects - minimal impact on PCIe performance, slight increase in jitter (still within spec). When to enable: Always enable for production systems to ensure EMC compliance. Disable only for testing or debugging. The down-spread modulation centers the average frequency at the nominal value. PCIe devices are designed to tolerate spread spectrum clocks.
Enable spread spectrum for production to ensure EMC compliance.
What is HCSL output and how do I interface with it?
HCSL (High-Speed Current Steering Logic) is the standard output for PCIe clocks: Differential output - provides positive (CLK+) and negative (CLK-) signals. Low voltage swing - 0.7V to 1.2V differential swing. Current mode - 14mA current source, requires termination. Termination - 50 ohms to ground at receiver end. Benefits: Low EMI, good signal integrity, PCIe compatible. Interfacing: Connect CLK+ to PCIe device clock input positive. Connect CLK- to PCIe device clock input negative. Place 50 ohm termination resistors near the receiver. Keep trace lengths matched and short (<6 inches). HCSL is the industry standard for PCIe reference clocks and is supported by all PCIe devices.
Use standard HCSL termination at receiver. Contact us for layout recommendations.
Can I use this clock generator for non-PCIe applications?
Yes, this clock generator can be used for non-PCIe applications: General 100MHz clocking - HCSL can be converted to single-ended if needed. High-speed serial - suitable for SATA, USB3, Ethernet with proper termination. FPGA clocking - many FPGAs accept differential clocks. Processor clocking - check specific processor requirements. Considerations: Output is 100MHz fixed frequency. HCSL output level may need translation for CMOS inputs. Spread spectrum may not be desired for some applications. For non-PCIe use, verify: Input frequency requirements, Output level compatibility, Jitter requirements. The excellent jitter performance makes this suitable for many high-speed applications beyond PCIe.
Verify compatibility with your specific application requirements.
What power supply decoupling is required?
Power supply decoupling for this clock generator: 3.3V VDD pins - 0.1uF ceramic capacitor per pin, placed close to pin. Bulk decoupling - 1uF to 10uF near the device. Ground connections - solid ground plane, multiple vias to ground. Layout recommendations: Keep decoupling capacitors within 2mm of power pins. Use short, wide traces for power distribution. Avoid vias in high-frequency current paths. Separate analog and digital grounds if applicable. Filter noise - consider ferrite bead for noisy systems. The clock generator is sensitive to power supply noise. Good decoupling ensures low jitter and stable operation. Follow the evaluation board layout for best performance.
Use 0.1uF per power pin plus bulk capacitance. Contact us for layout review.