Tang Dynasty Software Tutorial
Tang Dynasty (TD) is Anlogic's comprehensive FPGA development environment, providing design entry, synthesis, implementation, and programming capabilities. This tutorial covers the essential workflow from project creation to device programming.
Installation of TD software is straightforward. Download the installer from Anlogic website or request from BeiLuo. The software requires Windows 7 or later with minimum 4GB RAM. For large designs, 16GB RAM is recommended. Installation includes device support packages, IP libraries, and programming tools.
Creating a new project in TD involves selecting the target device, setting project directories, and adding source files. TD supports Verilog, VHDL, and SystemVerilog for design entry. The project wizard guides through initial setup with device selection from the comprehensive Anlogic portfolio.
The design flow in TD follows standard FPGA methodology: synthesis converts HDL to gate-level netlist, placement assigns logic to physical device resources, routing connects the placed logic, and bitstream generation creates the programming file. TD provides detailed reports at each stage for design analysis.
Debugging capabilities in TD include integrated logic analyzer for real-time signal observation, timing analyzer for performance verification, and power analyzer for thermal estimation. The TD programmer tool supports JTAG and SPI configuration modes with fast programming speeds.
💡 FAE Insights
⚠️ Common Pitfalls
- ✗ Insufficient RAM causing long compile times
- ✗ Not using proper constraint files
- ✗ Ignoring timing warnings during synthesis
📋 Customer Cases
Embedded Systems Inc.
Embedded Systems
Challenge
Team was familiar with Xilinx tools but needed to learn TD software for new Anlogic-based project. Required training and support.
Solution
BeiLuo provided TD software training sessions and hands-on workshops. Created custom tutorial based on customer's specific application requirements.
Results
Development team became proficient in TD within 2 weeks. First prototype completed in 4 weeks. Design achieved timing closure on first attempt.