How to Select the Right ADC for Your Application
Selecting the right Analog-to-Digital Converter (ADC) is critical for system performance. This guide walks through the key selection criteria for different ADC architectures.
Understanding ADC Architectures
Analog Devices offers three primary ADC architectures, each optimized for different applications:
SAR ADCs (Successive Approximation Register)
SAR ADCs provide the best balance of speed, power, and resolution for general-purpose applications. They excel in:
- Multiplexed systems where multiple channels need to be sampled sequentially
- Control loops requiring low latency (typically 1-5μs conversion time)
- Battery-powered applications where power scales with sampling rate
- Resolutions from 8-bit to 20-bit, with speeds up to 10MSPS
Key ADI SAR ADC families: AD400x (high precision), AD7606 (multichannel), AD798x (low power)
Sigma-Delta ADCs
Sigma-Delta ADCs use oversampling and noise shaping to achieve very high resolution (up to 32 bits). They are ideal for:
- Precision measurement applications requiring high dynamic range
- Sensor interfaces (RTDs, thermocouples, bridge sensors)
- Audio and vibration analysis
- Applications where integrated signal conditioning simplifies design
Key ADI Sigma-Delta families: AD7124 (low power), AD717x (high speed), AD776x (precision)
Pipeline ADCs
Pipeline ADCs achieve the highest sampling rates (up to GSPS) for communications and imaging:
- High-speed communications (5G, satellite, radar)
- Medical imaging (CT, MRI)
- Video and display applications
- Test and measurement equipment
Key ADI Pipeline families: AD9208 (14-bit 3GSPS), AD9689 (16-bit 2GSPS)
Selection Criteria
Resolution and Dynamic Range
Resolution determines the smallest signal change that can be detected. Consider:
- Signal-to-Noise Ratio (SNR) requirements
- Total Harmonic Distortion (THD) for AC signals
- Effective Number of Bits (ENOB) - often 2-3 bits less than nominal resolution
- Spurious-Free Dynamic Range (SFDR) for communications
Sampling Rate
Follow the Nyquist criterion: sample at least 2× the highest frequency of interest. Practical considerations:
- Oversampling improves SNR by 3dB (0.5 bit) per doubling
- Anti-aliasing filter requirements ease with higher sampling rates
- System timing and latency requirements
Interface Considerations
ADC interface options include:
- SPI/I2C: Simple, low pin count, suitable for < 10MSPS
- Parallel: Fast, but requires many IO pins
- JESD204B/C: High-speed serial, standard for GSPS ADCs
Application-Specific Recommendations
Industrial Sensor Interface
For RTD and thermocouple measurement, the AD7124-4 offers:
- 24-bit resolution with integrated PGA
- Programmable excitation currents for ratiometric measurement
- 50/60Hz rejection for industrial environments
- Ultra-low power (9.5μA in standby)
Multichannel Data Acquisition
For power monitoring and motor control, the AD7606 provides:
- 8-channel simultaneous sampling
- ±10V true bipolar inputs
- 16-bit resolution at 200kSPS per channel
- Integrated protection and signal conditioning
Software-Defined Radio
For SDR applications, the AD9208 delivers:
- 14-bit resolution at 3GSPS
- JESD204B interface for FPGA connectivity
- Excellent SFDR for communications
- Integrated DDC for bandwidth reduction
💡 FAE Insights
⚠️ Common Pitfalls
- ✗ Selecting ADC based only on resolution without considering ENOB
- ✗ Inadequate anti-aliasing filter design
- ✗ Poor PCB layout causing ground loops and noise coupling
- ✗ Insufficient reference decoupling
- ✗ Ignoring thermal effects on offset and drift
📋 Customer Cases
Industrial Automation Corp
Industrial
Challenge
Existing 12-bit ADC system couldn't provide sufficient resolution for harmonic analysis to meet IEC 61000-4-30 Class A requirements
Solution
Upgraded to AD7606 16-bit simultaneous sampling ADC with custom FPGA processing for real-time harmonic analysis
Customer Feedback
"Achieved Class A compliance with 91dB SNR, deployed in 200+ substations with 99.9% uptime over 3 years. The customer reported excellent performance and reliability."
Frequently Asked Questions
1. What is the difference between resolution and ENOB?
Resolution is the number of bits the ADC outputs, while ENOB (Effective Number of Bits) is the actual dynamic performance accounting for noise and distortion. ENOB is calculated from SNR: ENOB = (SNR - 1.76) / 6.02. For example, a 16-bit ADC might have 14.5 ENOB at high frequencies due to noise. Factors reducing ENOB include: clock jitter, reference noise, thermal noise, and quantization error. When selecting an ADC, always check the ENOB specification for your operating frequency, not just the nominal resolution. For DC measurements, ENOB is typically close to nominal resolution. For AC signals at high frequencies, ENOB can be 2-3 bits less than nominal resolution.
2. How do I calculate the required sampling rate?
Sampling rate selection follows Nyquist: sample at least 2× the highest frequency of interest. However, practical designs benefit from oversampling: 1) Anti-aliasing filter design is easier with higher sampling rates; 2) Oversampling improves SNR by 3dB (0.5 bit) per doubling of sample rate; 3) Sigma-Delta ADCs require high oversampling ratios (64x-256x). For example: Audio (20kHz bandwidth): 48-96kSPS; Industrial sensors (1kHz): 10-100kSPS; Communications (10MHz): 25-40MSPS. Include 20-30% margin for future requirements. If your signal has high-frequency content you don't need, consider using an anti-aliasing filter to prevent aliasing, or select an ADC with built-in digital filtering.
3. What clock jitter can my application tolerate?
Clock jitter limits the achievable SNR at high frequencies. The formula is: SNR_jitter = -20×log10(2×π×f_in×t_jitter), where f_in is input frequency and t_jitter is clock jitter. For example, with 1ps jitter at 100MHz: SNR = -20×log10(2×π×100e6×1e-12) = 64dB (about 10.3 ENOB). Applications have different jitter requirements: Audio (< 20kHz): > 1ns jitter acceptable; Industrial (100kHz): < 100ps; Communications (1GHz): < 100fs; High-speed ADCs (> 1GSPS): < 50fs. Use low-jitter crystal oscillators or PLLs for clock generation. ADI offers clock distribution ICs like the AD951x series with < 100fs jitter. Always use proper clock buffering and termination to prevent additional jitter.
4. How do I drive a high-resolution ADC properly?
Driving high-resolution ADCs (16-24 bit) requires careful attention: 1) Amplifier selection - choose op-amp with bandwidth > 10× ADC sampling rate, noise < 1/2 LSB, and fast settling; 2) Anti-aliasing filter - place between amplifier and ADC with cutoff at 0.5× sampling rate; 3) Charge kickback - add isolation resistor (10-100Ω) between amplifier and ADC to prevent instability from ADC input capacitance; 4) Output swing - ensure amplifier can drive to within 100mV of ADC reference rails; 5) Settling time - amplifier must settle to 0.0015% for 16-bit or 0.00006% for 24-bit within acquisition time. ADI provides specific ADC driver recommendations in datasheets. Use LTspice to simulate the complete driver-ADC interface before building.
5. What reference voltage should I use?
Reference voltage selection impacts ADC accuracy: 1) Initial accuracy - use 0.1% or better tolerance for absolute accuracy; 2) Temperature drift - select < 10ppm/°C for industrial applications; 3) Noise - reference noise adds directly to ADC noise, choose < 10μVp-p; 4) Load regulation - ensure reference maintains accuracy under ADC reference current transients; 5) Long-term stability - important for calibration-free operation. ADI precision references: ADR43xx series (3-5ppm/°C), ADR45xx series (1-2ppm/°C), LT6657 (ultra-low noise). For highest accuracy, use the ADC's internal reference if available, or buffer external references with precision op-amp. Place decoupling capacitors (0.1μF + 10μF) close to ADC reference pins. For ratiometric measurement (like RTDs), use the same reference for sensor excitation and ADC reference to cancel drift.