ADF4351

The ADF4351 uses a fractional-N PLL with INT and FRAC registers to set output frequency. The formula is: Fout = (INT + FRAC/MOD) × Fpfd, where Fpfd = REFIN × (1 + D) / (R × (1 + T)), D is reference doubler (0 or 1), R is reference divider (1 to 1023), and T is reference divide-by-2 (0 or 1). Example for 2.1GHz output with 25MHz reference: Set D=0, R=1, T=0, so Fpfd = 25MHz. Choose MOD = 100 for 250kHz channel spacing. INT = floor(2100/25) = 84, FRAC = round((2100/25 - 84) × 100) = 0. So INT=84, FRAC=0, MOD=100. For 2.125GHz: INT=85, FRAC=0. For 2.1375GHz: INT=85, FRAC=50. ADI provides ADIsimPLL software that calculates all register values automatically and simulates phase noise performance.

Use ADIsimPLL software for automatic register calculation; formula: Fout = (INT + FRAC/MOD) × Fpfd.

The ADF4351 reference input can be 10MHz to 250MHz. Reference frequency selection involves trade-offs: Lower reference (10-25MHz): better phase noise close to carrier (inside PLL bandwidth), finer frequency resolution with same MOD value, but slower lock time. Higher reference (50-100MHz): faster lock time, wider PLL bandwidth possible, but coarser frequency resolution and potentially worse close-in phase noise. For most applications, 25MHz or 50MHz are good choices. Use a TCXO (temperature-compensated crystal oscillator) for moderate stability requirements (±1-2ppm), or OCXO (oven-controlled) for high stability (±0.01-0.1ppm). The reference phase noise directly affects output phase noise inside the PLL bandwidth. For best performance, use a low-noise reference with < -140dBc/Hz at 1kHz offset. ADI recommends the AD9548 for high-performance reference generation.

Use 25-50MHz for most apps; use TCXO for moderate stability, OCXO for high stability; ensure low phase noise reference.

Spurious outputs in fractional-N PLLs include: integer boundary spurs (when Fout is close to integer multiple of Fpfd), fractional spurs (at multiples of Fpfd/MOD), and reference spurs (at multiples of Fpfd). Minimization techniques: 1) Avoid integer boundary - if possible, shift frequency by > 5× PLL bandwidth from integer boundary; 2) Use low spur mode - ADF4351 has fast-lock and low-noise modes; 3) Optimize loop filter - narrower bandwidth reduces spurs but increases lock time; 4) Use higher MOD value - spreads fractional spurs over wider frequency range; 5) Ensure clean reference - reference spurs are directly related to reference quality; 6) Proper PCB layout - isolate sensitive analog sections from digital noise. Integer boundary spurs can be particularly problematic - if your application requires frequencies near integer boundaries, consider using a different reference frequency to shift the boundary away from your operating frequency.

Avoid integer boundaries; use low spur mode; optimize loop filter bandwidth; ensure clean reference and good PCB layout.

The ADF4351 lock time depends on PLL bandwidth and frequency step size: Typical lock time is < 1ms for small frequency steps (< 100MHz) with 100kHz loop bandwidth. For fast-lock applications, the ADF4351 supports a fast-lock mode that reduces lock time to < 100μs: Fast-lock mode uses wider bandwidth during frequency change, then switches to narrow bandwidth for operation. To use fast-lock: 1) Program wide bandwidth during acquisition (higher charge pump current, wider loop filter); 2) Use timer or lock detect to switch to narrow bandwidth after lock; 3) Alternatively, use cycle slip reduction feature. Lock time increases with: larger frequency steps, narrower PLL bandwidth, and lower charge pump current. For frequency hopping applications, use fast-lock mode or cycle slip reduction. The digital lock detect output can be used to trigger external circuitry when lock is achieved.

Normal mode: < 1ms lock time; Fast-lock mode: < 100μs; use fast-lock for frequency hopping applications.

The ADF4351 has two RF outputs (RFoutA and RFoutB) that can operate simultaneously with some limitations: RFoutA can output the fundamental VCO frequency (2.2-4.4GHz) or divided versions (using on-chip dividers: /2, /4, /8, /16, /32, /64). RFoutB can output the fundamental VCO frequency only (2.2-4.4GHz). Both outputs are derived from the same VCO, so they are phase-coherent and cannot be at independent frequencies. For multiple independent frequencies, you need multiple ADF4351 devices. However, the dual outputs are useful for: 1) Providing both fundamental and divided outputs simultaneously (e.g., 2.4GHz on RFoutB and 1.2GHz on RFoutA with /2 divider); 2) Driving multiple signal chains with the same frequency; 3) Providing differential outputs for balanced systems. Each output has independent enable control and programmable output power level (from -4dBm to +5dBm).

Two outputs from same VCO (phase-coherent); RFoutA supports dividers, RFoutB is fundamental only; for independent frequencies use multiple devices.