AD9361
Highly integrated RF transceiver covering 70MHz-6GHz with 200kHz-56MHz bandwidth for software-defined radio.
Product Overview
Description
The AD9361 is a high-performance, highly integrated RF Agile Transceiver™ that combines RF front-end, mixed-signal processing, and frequency synthesis in a single device. It covers a frequency range of 70MHz to 6GHz with channel bandwidths from 200kHz to 56MHz.
The device features dual independent transmitters and receivers with flexible frequency synthesis and digital filtering. The integrated frequency synthesizers use fractional-N PLLs with industry-leading phase noise performance.
The AD9361 interfaces to baseband processors via a flexible digital interface supporting JESD204B high-speed serial or CMOS parallel modes. The device is programmable through a simple SPI interface and includes automatic gain control (AGC) and DC offset correction.
Product Series
AD
Primary Application
Software-defined radio (SDR)
Key Features
- Dual independent transmitters and receivers
- Wide frequency coverage (70MHz - 6GHz)
- Adjustable channel bandwidth (200kHz - 56MHz)
- Fractional-N frequency synthesis
- Integrated AGC and DC offset correction
- Flexible digital interface (JESD204B/CMOS)
- Fast frequency hopping (< 200μs)
- Low power consumption (1.3W typical)
Specifications
| Frequency Range | 70MHz to 6GHz |
|---|---|
| Bandwidth | 200kHz to 56MHz |
| Tx Output Power | 7dBm max |
| Rx Noise Figure | 2dB at 800MHz |
| Rx Gain Range | 73dB |
| Tx Attenuation Range | 89.75dB |
| Phase Noise | -140dBc/Hz at 1MHz offset |
| Interface | JESD204B or CMOS |
| Supply Voltage | 1.3V, 1.8V, 3.3V |
| Package | 12mm × 12mm BGA |
| Temperature Range | -40°C to +85°C |
Applications
Software-defined radio (SDR)
Electronic system design
3G and 4G small cell base stations
Electronic system design
Point-to-point communication systems
Communication and interface
Military communications
Communication and interface
Public safety radios
Electronic system design
General-purpose RF systems
Electronic system design
FAE Expert Insights
"The AD9361 revolutionized software-defined radio when it was introduced - integrating an entire RF transceiver into a single chip was unprecedented. I've used it in numerous SDR projects from 70MHz HF up to 6GHz WiFi bands. The performance is excellent: 2dB noise figure is competitive with discrete designs, and the phase noise is good enough for most communications standards. The integrated AGC works well, though I prefer manual gain control for some applications. The JESD204B interface is high-speed but requires FPGA support - ADI provides excellent reference HDL for Xilinx and Intel FPGAs. One limitation is the 56MHz bandwidth - for wider bandwidths, look at ADRV9009. The power consumption (1.3W) is reasonable for the performance. The learning curve is steep but ADI's documentation and community support are excellent. Overall, the AD9361 remains the gold standard for integrated SDR transceivers."
Unprecedented integration for SDR; 2dB NF competitive with discrete; excellent FPGA reference designs provided
— Alex Thompson, BeiLuo
Frequently Asked Questions
What FPGA is recommended for AD9361 interface?
The AD9361 interfaces via JESD204B high-speed serial interface requiring FPGA transceivers. Recommended FPGAs: Xilinx Zynq-7000 series (ZC706, ZedBoard) - ADI provides complete reference designs including HDL and Linux drivers; Xilinx Artix-7 (AC701) - lower cost option for simpler applications; Intel Cyclone V SoC - supported with reference designs; Xilinx Kintex-7 (KC705) - for high-performance applications. The FPGA must have: GTX or GTH transceivers for JESD204B (2.5-6Gbps per lane); sufficient logic resources for digital signal processing (50K+ LUTs recommended); DDR3 memory interface for data buffering. ADI's reference designs include: HDL for JESD204B interface, Linux device drivers, no-OS drivers for bare-metal, MATLAB/Simulink models, and example applications. For beginners, start with the ZedBoard or ZC706 evaluation platforms which include complete reference designs.
Use Zynq-7000 for best support; requires GTX/GTH transceivers; ADI provides complete HDL and software reference designs.
What is the power consumption of AD9361?
The AD9361 power consumption depends on operating mode and configuration: Full-duplex mode (Tx + Rx active): approximately 1.3W typical; Receive-only mode: approximately 0.7W; Transmit-only mode: approximately 0.9W; Sleep/standby mode: < 1mW. Power breakdown: RF front-end: ~40%; ADC/DAC: ~30%; Frequency synthesizers: ~20%; Digital: ~10%. Power consumption scales with: Sampling rate (higher rate = more power); Number of active channels; PLL output frequency (higher frequency = more power); Digital interface speed. For battery-powered applications, use the fast power-down modes between transmissions. The device can wake from sleep to full operation in < 200μs. Power supply requirements: 1.3V (analog), 1.8V (digital), 3.3V (I/O). Use separate regulators for each rail with proper filtering for best performance.
1.3W typical in full-duplex; 0.7W Rx-only; < 1mW sleep mode; use power-down between transmissions for battery apps.
How do I program the AD9361?
The AD9361 is programmed via SPI interface with register writes to configure all operating parameters: Initialization sequence: 1) Apply power and wait for supplies to stabilize; 2) Perform digital reset; 3) Load initial register settings from reference configuration; 4) Calibrate internal blocks (BBPLL, RFPLL); 5) Enable desired signal paths. Key configuration parameters: LO frequency (set via RFPLL registers); Baseband filter bandwidth; Sampling rate (set via BBPLL); Tx attenuation and Rx gain; DC offset correction settings. ADI provides: no-OS C driver library with API functions; Linux IIO drivers; MATLAB control scripts; Evaluation software (IIO Oscilloscope). The easiest approach is to start with ADI's reference configuration for your frequency band, then modify specific parameters. The IIO Oscilloscope GUI allows real-time adjustment and visualization of all parameters. For custom applications, use the no-OS driver as a starting point.
Use SPI interface; start with ADI reference configs; use no-OS driver or Linux IIO; IIO Oscilloscope for evaluation.
What is the minimum frequency of AD9361?
The AD9361 is specified for 70MHz to 6GHz operation, but it can operate below 70MHz with some limitations. The RF PLL can tune down to approximately 47MHz, but performance degrades below 70MHz: Noise figure increases below 70MHz; Phase noise performance degrades; Image rejection may not meet specifications; DC offset correction may have issues near DC. For applications below 70MHz (HF, LF bands), options include: 1) Use external upconversion/downconversion to shift signals into the 70MHz-6GHz range; 2) Use the AD9361 with reduced performance expectations below 70MHz; 3) Consider the ADRV9009 which has better low-frequency performance; 4) Use discrete RF components for sub-70MHz and AD9361 for higher frequencies. Many users successfully operate the AD9361 down to 50-60MHz for amateur radio and ISM band applications, but ADI only guarantees specifications above 70MHz.
Specified for 70MHz-6GHz; can operate to ~47MHz with degraded performance; use external conversion for HF bands.
Can AD9361 support MIMO applications?
Yes, the AD9361 supports 2x2 MIMO (Multiple Input Multiple Output) configurations. A single AD9361 contains 2 transmitters and 2 receivers that can operate simultaneously, providing a complete 2x2 MIMO solution. For larger MIMO arrays (4x4, 8x8, 64x64), multiple AD9361 devices can be synchronized: Synchronization method: 1) Share a common reference clock (XTAL or external) between all devices; 2) Distribute a common BBPLL reference to ensure coherent sampling; 3) Use common ENABLE and TXNRX signals for synchronized operation; 4) Phase-align LO signals using external distribution or ADI's phase synchronization feature. ADI provides reference designs for: 2x2 MIMO (single AD9361); 4x4 MIMO (two AD9361s); 8x8 MIMO (four AD9361s). For massive MIMO applications (64x64), consider the ADRV9009 which supports up to 8 channels per device. The JESD204B interface supports multi-device synchronization for coherent operation across the array.
Single AD9361 provides 2x2 MIMO; sync multiple devices for larger arrays; use common reference clock and enable signals.