ADP1741
Low noise, high PSRR LDO with 1.6A output current, 1.6V to 3.6V input range, and excellent transient response.
Product Overview
Description
The ADP1741 is a high-performance low-dropout linear regulator featuring low noise, high power supply rejection ratio (PSRR), and excellent transient response. It delivers up to 1.6A output current from a 1.6V to 3.6V input supply.
The device achieves 65dB PSRR at 100kHz and 50dB at 1MHz, making it ideal for post-regulation after switching converters. Output noise is just 35μVrms from 10Hz to 100kHz, suitable for noise-sensitive RF and precision analog circuits.
With a low dropout voltage of 150mV at 1.6A load, the ADP1741 maximizes battery life in portable applications. The device features an adjustable output from 0.75V to 3.3V set by external resistor divider.
Product Series
ADP
Primary Application
Post-regulation for switching supplies
Key Features
- High PSRR for noise-sensitive applications
- Ultra-low output noise (35μVrms)
- Low dropout voltage (150mV at 1.6A)
- Excellent load/line transient response
- Adjustable output voltage
- Current limit and thermal protection
- Logic-controlled shutdown
- Stable with small ceramic capacitors
Specifications
| Input Voltage | 1.6V to 3.6V |
|---|---|
| Output Voltage | 0.75V to 3.3V (adjustable) |
| Output Current | 1.6A max |
| Dropout Voltage | 150mV at 1.6A |
| PSRR | 65dB at 100kHz, 50dB at 1MHz |
| Output Noise | 35μVrms (10Hz-100kHz) |
| Quiescent Current | 1.2mA |
| Shutdown Current | 1μA |
| Load Regulation | 0.3% from 10mA to 1.6A |
| Package | LFCSP-8, SOIC-8 |
| Temperature Range | -40°C to +125°C |
Applications
Post-regulation for switching supplies
Power conversion and supply
RF and PLL power supplies
Electronic system design
High-resolution ADC/DAC supplies
Data acquisition and conversion
Medical imaging equipment
Medical electronics
Communications infrastructure
Communication and interface
Portable battery-powered devices
Battery and charging management
FAE Expert Insights
"The ADP1741 is my go-to LDO for noise-sensitive applications requiring moderate current. The 65dB PSRR at 100kHz is excellent for filtering switching regulator ripple - I've used it after buck converters to supply clean power to 16-bit ADCs with excellent results. The 35μVrms noise is among the best in its class. The transient response is remarkably fast - it handles load steps from 10mA to 1A with minimal undershoot, critical for FPGA core supplies. The 150mV dropout at 1.6A is reasonable, allowing efficient operation from 3.3V input down to 2.5V output. One feature I appreciate is stability with ceramic capacitors - no need for ESR requirements. The adjustable version provides flexibility, though fixed voltage versions are available for common rails. For higher current (up to 2A), consider the ADP1755. Overall, an excellent low-noise LDO for precision analog and RF applications."
65dB PSRR at 100kHz excellent for post-regulation; 35μVrms noise; fast transient response for FPGA supplies
— Jennifer Park, BeiLuo
Frequently Asked Questions
What is the dropout voltage of ADP1741?
The ADP1741 dropout voltage is the minimum input-to-output voltage differential required to maintain regulation. At 1.6A output current, typical dropout is 150mV, maximum is 200mV. At lighter loads, dropout is lower: approximately 100mV at 1A, 50mV at 500mA, and 20mV at 100mA. The dropout voltage increases slightly at higher temperatures. For proper regulation, maintain Vin ≥ Vout + Vdropout. Example: for 2.5V output at 1.6A, minimum input is 2.5V + 0.15V = 2.65V. The dropout is determined by the RDS(on) of the internal pass transistor. The ADP1741 uses a PMOS pass device for low dropout. For applications requiring even lower dropout, consider devices with NMOS or charge pump architectures, though these typically have higher quiescent current.
Dropout is 150mV at 1.6A; ensure Vin ≥ Vout + 150mV for regulation; decreases at lighter loads.
How do I calculate power dissipation in ADP1741?
LDO power dissipation is calculated as: Pdiss = (Vin - Vout) × Iout + Vin × Iq, where Iq is quiescent current (1.2mA typical). The quiescent term is usually negligible compared to load-dependent dissipation. Example calculations: 1) Vin=3.3V, Vout=2.5V, Iout=1A: Pdiss = (3.3-2.5) × 1 + 3.3 × 0.0012 = 0.8 + 0.004 = 0.804W; 2) Vin=3.3V, Vout=1.8V, Iout=1.6A: Pdiss = (3.3-1.8) × 1.6 + 0.004 = 2.4W. Thermal considerations: Junction temperature Tj = Ta + (Pdiss × θja). For LFCSP-8, θja is approximately 50°C/W on standard board. At 25°C ambient with 0.8W dissipation: Tj = 25 + (0.8 × 50) = 65°C. At 2.4W: Tj = 25 + (2.4 × 50) = 145°C, exceeding the 125°C limit. For high dissipation applications, use larger copper area, thermal vias, heat sinks, or reduce input voltage.
Pdiss = (Vin-Vout) × Iout; calculate Tj = Ta + (Pdiss × θja); ensure Tj < 125°C; use thermal management for > 1W.
What capacitors are recommended for ADP1741?
The ADP1741 is stable with ceramic capacitors and requires minimum 4.7μF output capacitance with ESR < 500mΩ. Recommended configuration: Input capacitor: 4.7μF to 10μF ceramic (X5R or X7R) placed close to VIN pin; Output capacitor: 4.7μF to 22μF ceramic (X5R or X7R) placed close to VOUT pin; Additional bulk capacitance: 100μF electrolytic or tantalum at output for large load transients. For best PSRR and transient response, use larger output capacitance (22μF or more). The capacitor voltage rating should be at least 1.5x the operating voltage. Use X7R dielectric for best temperature stability. Avoid Y5V capacitors due to poor DC bias characteristics. Place capacitors as close to the IC as possible with short, wide traces. A 0.1μF bypass capacitor at the input can help with high-frequency noise.
Use 4.7-22μF ceramic output cap; 4.7-10μF input cap; X5R/X7R dielectric; place close to IC.
How do I set the output voltage on ADP1741?
The adjustable version ADP1741 sets output voltage via resistor divider from VOUT to FB pin to ground. The feedback reference voltage is 0.5V. The output voltage equation is: Vout = 0.5V × (1 + R1 / R2), where R1 is top resistor and R2 is bottom resistor. Design procedure: 1) Choose R2 in range 10kΩ to 100kΩ (typically 10kΩ for lower noise); 2) Calculate R1 = R2 × (Vout / 0.5V - 1); 3) Use standard 1% resistor values. Example for 2.5V output: R2 = 10kΩ, R1 = 10k × (2.5/0.5 - 1) = 40kΩ. Use 40.2kΩ standard value. For 1.8V output: R1 = 10k × (1.8/0.5 - 1) = 26kΩ. Use 26.1kΩ standard value. Place resistors close to FB pin with short traces. Add 10pF-100pF feedforward capacitor across R1 to improve transient response. For fixed output voltages (1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V), use the ADP1740 fixed versions which don't require external resistors.
Use Vout = 0.5V × (1 + R1/R2); R2 typically 10kΩ; use 1% resistors; add feedforward cap for better transient.
What is the PSRR of ADP1741 and why does it matter?
PSRR (Power Supply Rejection Ratio) indicates how well the LDO rejects ripple and noise from the input supply. The ADP1741 PSRR is: 80dB at 1kHz, 65dB at 100kHz, 50dB at 1MHz, 35dB at 10MHz. This means at 100kHz, input ripple is attenuated by 65dB (a factor of 1778). Example: If the input has 100mV ripple at 100kHz from a switching regulator, output ripple is 100mV / 1778 = 56μV. This is excellent for powering noise-sensitive circuits like ADCs, DACs, and RF components. High PSRR is critical when the LDO is used for post-regulation after a switching converter. The PSRR degrades at higher frequencies, so additional filtering may be needed for very sensitive applications. For best PSRR performance: use sufficient output capacitance (22μF or more), minimize trace inductance between input cap and LDO, and ensure good grounding.
65dB PSRR at 100kHz; excellent for post-regulation; use 22μF+ output cap for best PSRR; degrades at higher frequencies.